Low-Power Cache Design Using 7T SRAM Cell

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 4, 2007, Pages 318-322

  Aly, Ramy E ^a   Bayoumi, Magdy A ^a  

^a UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

Author keywords

Low power; on chip cache; SRAM cell

Indexed keywords

CACHE MEMORY; CAPACITANCE; CHIP SCALE PACKAGES; CIRCUIT SIMULATION; SPICE; TRANSISTORS;

ON-CHIP CACHE; READ DELAY; STATIC NOISE MARGIN;

STATIC RANDOM ACCESS STORAGE;

EID: 34247367942     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.877276     Document Type: Article

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