Single-ended subthreshold SRAM with asymmetrical write/read-assist

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 12, 2010, Pages 3039-3047

  Tu, Ming Hsien ^a   Lin, Jihi Yu ^a   Tsai, Ming Chien ^a   Jou, Shyh Jye ^a   Chuang, Ching Te ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Low power; low voltage; single ended SRAM

Indexed keywords

ELECTRICAL ENGINEERING; ELECTRONICS ENGINEERING;

BIASING SCHEME; LOW POWER; LOW VOLTAGES; OPERATION FREQUENCY; OPERATION SPEED; READ STATIC NOISE MARGIN (RSNM); SINGLE-ENDED; SUB-THRESHOLD SRAM;

FEEDBACK;

EID: 78650305296     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2010.2071690     Document Type: Article

References (24)

1. B. H. Calhoun and A. P. Chandrakasan, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1673-1679, Jul. 2006.
2. B. H. Calhoun and A. P. Chandrakasan, "A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation," IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 680-688, Mar. 2007.
3. B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, "A variation-tolerant sub-200 mV 6-T subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2338-2348, Oct. 2008.
4. M. Sharifkhani and M. Sachdev, "An energy efficient 40 Kb SRAM module with extended read/write noise margin in 0.13 um CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 620-630, Feb. 2009.
5. T.-H. Kim, J. Liu, J. Keane, and C. H. Kim, "A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 518-529, Feb. 2008.
6. I. J. Chang, J. J. Kim, S. P. Park, and K. Roy, "A 32 kb 10 T subthreshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS," in ISSCC Dig. Tech. Papers, Feb. 3-7, 2008, pp. 388-622.
7. J. Y. Lin, M. H. Tu,M. C. Tsai, S. J. Jou, and C. T. Chuang, "Asymmetrical write-assist for single-ended SRAM operation," in Proc. SOCC, Sep. 9-11, 2009, pp. 101-104.
8. S. T. Eid, M. Whately, and S. Krishnegowda, "A microcontroller-based PVT control system for a 65 nm72Mb synchronous SRAM," in ISSCC Dig. Tech. Papers, Feb. 7-11, 2010, pp. 184-185.
9. M. F. Chang, S. M.Yang, and K. T. Chen, "Wide V dd embedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp. 1657-1667, Aug. 2009.
10. S. C. Luo and L. Y. Chiou, "A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 6, pp. 440-445, Jun. 2010.
11. C. T. Chuang, S. Mukhopadhyay, J. J. Kim, K. Kim, and R. Rao, "Highperformance SRAM in nanoscale CMOS: Design challenges and techniques," in IEEE Int. Workshop Memory Technol., Des. Testing, Dec. 3-5, 2007, pp. 4-12.
12. M. Yabuuch et al., "A 45 nm low-standby-power embedded SRAM with improved immunity against process and temperature variations," in ISSCC Dig. Tech. Papers, 2007, pp. 326-327.
13. K. Takeda et al., "A read-static-noise-margin-free SRAM cell for low-Vdd and high-speed applications," in ISSCC Dig. Tech. Papers, 2005, pp. 478-479.
14. L. Chang et al., "Stable SRAM cell design for the 32 nm node and beyond," in Symp. VLSI Technol. Dig. Tech. Papers, 2005, pp. 128-129.
15. J. Chen, L. T. Clark, and T. Chen, "An ultra-low-power memory with a subthreshold power supply voltage," IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2344-2353, Oct. 2006.
16. R. F. Hobson, "A new single-ended SRAM cell with write-assist," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 2, pp. 173-181, Feb. 2007.
17. H. I. Yang, M. H. Chang, S. Y. Lai, H. F. Wang, and W. Hwang, "A low-power low-swing single-ended multi-port SRAM," in Proc. VLSIDAT, 2007, pp. 28-31.
18. A. Sil, S. Ghosh, and M. Bayoumi, "A novel 90 nm8 T SRAMcell with enhanced stability," presented at the IEEE Int. Conf. Integr. Circuit Des. Technol. 2007 (ICICDT '07), Austin, TX.
19. H. Noguchi, S. Okumura, Y. Iguchi, H. Fujiwara, Y. Morita, K. Nii, H. Kawaguchi, and M. Yoshimoto, "Which is the best dual-port SRAM in 45-nm process technology?-8 T, 10 T single end, and 10 T differential-," in Proc. ICICDT, 2007, pp. 55-58.
20. T. Suzuki, H. Yamauchi, Y. Yamagami, K. Satomi, and H. Akamatsu, "A stable SRAM cell design against simultaneously R/W disturbed accesses," in Symp. VLSI Circuits Dig. Tech. Papers, 2006, pp. 11-12.
21. R. E. Aly and M. A. Bayoumi, "Low-power cache design using 7 T SRAM cell," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 4, pp. 318-322, Apr. 2007.
22. K. Kim, J. J. Kim, and C. T. Chuang, "Asymmetrical SRAM cells with enhanced read and write margins," in Proc. VLSI-TSA, 2007, pp. 162-163.
23. N. Verma and A. P. Chandrakasan, "A 65 nm 8 T sub-Vt SRAM employing sense-amplifier redundancy," in ISSCC Dig. Tech. Papers, Feb. 11-15, 2007, pp. 328-606.
24. T. H. Kim, J. Liu, J. Keane, and C. H. Kim, "A high-density subthreshold SRAM with data-independent bitline leakage and virtual ground replica scheme," in ISSCC Dig. Tech. Papers, Feb. 11-15, 2007, pp. 330-606.