Low power and robust 7T dual-Vt SRAM circuit

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 1452-1455

  Tawfik, Sherif A ^a   Kursun, Volkan ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; FLUIDIZED BED COMBUSTION; HAND HELD COMPUTERS; LEAKAGE CURRENTS; SPEED; SYSTEM STABILITY; TECHNICAL PRESENTATIONS; THRESHOLD VOLTAGE; TRANSISTORS;

CROSS-COUPLED; READ SPEED;

STATIC RANDOM ACCESS STORAGE;

EID: 51749118922     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541702     Document Type: Conference Paper

References (8)

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3. E. Seevinck, F. J. List, and J. Lohstroh, "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE Journal of Solid-State Circuits, Vol. 22, No. 5, pp. 748-754, October 1987.
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6. T. Devoivre et al., "Validated 90nm CMOS Technology Platform with Low-K Copper Interconnects for Advanced System-on-Chip (SOC)," Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing, pp. 157-162, July 2002.
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8. K. Zhang et al., "A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology with Integrated Column-Based Dynamic Power Supply," IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, pp.146-151, January 2006.