SCOPUS 정보 검색 플랫폼

Proceedings - IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, NDCS 2008

Volumn , Issue , 2008, Pages 17-20

A highly-stable nanometer memory for low-power design

(3) Lin, Sheng a Kim, Yong Bin a Lombardi, Fabrizio a

a Northeastern University (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CYTOLOGY; ELECTRIC POWER UTILIZATION; STATIC RANDOM ACCESS STORAGE; SYSTEM STABILITY; TECHNICAL PRESENTATIONS;

BIT LINES; ENERGY CONSUMPTIONS; FEATURE SIZES; HIGH DENSITIES; LOW POWERS; LOW-POWER MEMORIES; OPTIMUM SIZINGS; PARAMETER VARIATIONS; POWER CONSUMPTIONS; POWER DISSIPATIONS; POWER REDUCTIONS; PROCESS VARIATIONS; SRAM CELLS; T CELLS;

DESIGN;

EID: 56349157161 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/NDCS.2008.10 Document Type: Conference Paper

Times cited : (28)

References (8)

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- Chang, L.¹

2
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- B.H. Calhoun and A.P. Chandrakasan, A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation, Solid-State Circuits, IEEE Journal of, 42, Issue 3, March 2007, pp. 680-688.
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3
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- A Low Leakage 9T SRAM Cell for Ultra-Low Power Operation
- May
- S. Lin, Y-B. Kim, F. Lombardi, "A Low Leakage 9T SRAM Cell for Ultra-Low Power Operation", ACM Great Lakes Symposium on VLSI 2008, May 2008, pp. 123-126.
- (2008) ACM Great Lakes Symposium on VLSI 2008 , pp. 123-126
- Lin, S.¹ Kim, Y.-B.² Lombardi, F.³

4
- 85036612496
- IEEE Press
- A. Chandrakasan, W.J. Bowhill, F. Fox, "Design of High-Performance Microprocessor Circuits", IEEE Press, 2000.
- (2000) Design of High-Performance Microprocessor Circuits
- Chandrakasan, A.¹ Bowhill, W.J.² Fox, F.³

5
- 0023437909
- E. Seevinck, F.J. List, J. Lohstroh, Static-noise margin analysis of MOS SRAM cells, Solid-State Circuits, IEEE Journal of 22, Issue 5, Oct 1987, pp. 748-754.
- E. Seevinck, F.J. List, J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells", Solid-State Circuits, IEEE Journal of Volume 22, Issue 5, Oct 1987, pp. 748-754.

6
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- E. Grossar, M. Stucchi, K. Maex, W. Dehaene, Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies, Solid-State Circuits, IEEE Journal of, 41, Issue 11, Nov 2006, pp. 2577-2588.
- E. Grossar, M. Stucchi, K. Maex, W. Dehaene, "Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies", Solid-State Circuits, IEEE Journal of, Volume 41, Issue 11, Nov 2006, pp. 2577-2588.

7
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- Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model
- March
- S. M. Jahinuzzaman, M. Sharifkhani, M. Sachdev, "Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model", Quality Electronic Design, 2008. 9th International Symposium on, March 2008, pp. 207-212.
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- Jahinuzzaman, S.M.¹ Sharifkhani, M.² Sachdev, M.³

8
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- Berkeley Predictive Technology Model website

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