Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies

Electronics Letters

Volumn 46, Issue 4, 2010, Pages 273-274

  Azam, T ^a   Cheng, B ^a   Roy, S ^a   Cumming, D R S ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; COMPARATIVE ANALYSIS; LOW OVERHEAD; LOW-POWER CIRCUIT; LOW-POWER OPERATION; MONTE CARLO SIMULATION; NANO CMOS; SINGLE-ENDED; SRAM CELL; TOTAL POWER;

COMPUTER SIMULATION; LOGIC DESIGN; MONTE CARLO METHODS;

STATIC RANDOM ACCESS STORAGE;

EID: 77149164414     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el.2010.2817     Document Type: Article

References (7)

1. Cheng, B., Roy, S., Roy, G., Brown, A., and Asenov, A.: ' Impact of random dopant fluctuation on bulk CMOS 6-T SRAM scaling ', Proc. of 36th European Solid-State Device Research Conf., 2006, (ESSDERC 2006), Montreux, Switzerland, 2006
2. Singh, J., Pradhan, D., Hollis, S., and Mohanty, S.P.: ' A single ended 6T SRAM cell design for ultra-low-voltage applications ', IEICE Electron. Express, 2008, 5, (18), p. 750-755
3. Bo, Z., Hanson, S., Blaauw, D., and Sylvester, D.: ' A variation-tolerant sub-200mV 6-T subthreshold SRAM ', IEEE J. Solid-State Circuits, 2008, 43, (10), p. 2338-2348 0018-9200
4. Keunwoo, K., Jae-Joon, K., and Ching-Te, C.: ' Asymmetrical SRAM cells with enhanced read and write margins ', Int. Symp. VLSI Technology, Systems and Applications, 2007, (VLSI-TSA 2007), Hsinchu, Taiwan, 2007
5. Wang, X., Roy, S., and Asenov, A.: ' Impact of strain on the performance of high-k/metal replacement gate MOSFETs ', Proc. 10th Ultimate Integration on Silicon, (ULIS 2009), Aachen, Germany, 2009
6. Brown, A.R., Roy, G., and Asenov, A.: ' Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture ', IEEE Trans. Electron Devices, 2007, 54, (11), p. 3056-3063 0018-9383
7. Predictive Technology Models (PTM) are available online at: http://www.eas.asu.edu/~ptm/