An 8T differential SRAM with improved noise margin for bit-interleaving in 65 nm CMOS

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 58, Issue 6, 2011, Pages 1252-1263

  Anh Tuan, Do ^a   Low, Jeremy Yung Shern ^a   Low, Joshua Yung Lih ^a   Kong, Zhi Hui ^a   Tan, Xiaoliang ^b   Yeo, Kiat Seng ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b NONE

Author keywords

Low power SRAM; low voltage SRAM; multiple port SRAM; static noise margin free

Indexed keywords

CMOS INTEGRATED CIRCUITS; ERROR CORRECTION; LOGIC DESIGN; RADIATION HARDENING; STATIC RANDOM ACCESS STORAGE;

ERROR CORRECTING CODE; LOW-POWER SRAM; LOW-VOLTAGE SRAM; PARAMETER FLUCTUATIONS; READ NOISE MARGINS; SCALED TECHNOLOGIES; SOFT-ERROR TOLERANCE; STATIC NOISE MARGIN;

INTEGRATED CIRCUIT DESIGN;

EID: 79957965287     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2010.2103154     Document Type: Article

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