A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2011, Pages 291-296

  Chang, Ming Hung ^a   Chiu, Yi Te ^a   Lai, Shu Lin ^a   Hwang, Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

bit interleaving scheme; subthreshold SRAM; ultra low power

Indexed keywords

BIT LINES; BIT-INTERLEAVING; CMOS TECHNOLOGY; CUTTING-OFF; ENERGY-CONSTRAINED; MINIMUM ENERGY POINT; POSITIVE FEEDBACK LOOP; READ OPERATION; SOC DESIGNS; SOFT-ERROR TOLERANCE; STORAGE NODES; SUB-THRESHOLD SRAM; ULTRA-LOW POWER;

CMOS INTEGRATED CIRCUITS; DESIGN; ENERGY UTILIZATION; FEEDBACK; LOW POWER ELECTRONICS; POWER ELECTRONICS;

STATIC RANDOM ACCESS STORAGE;

EID: 80052756934     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2011.5993652     Document Type: Conference Paper

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