A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 1, 2011, Pages 85-96

  Qazi, Masood ^a   Stawiasz, Kevin ^b   Chang, Leland ^b   Chandrakasan, Anantha P ^a  

^a Massachusetts Institute of Technology Cambridge   (United States)

^b IBM   (United States)

Author keywords

Cache memories; CMOS memory circuits; leakage currents; low power electronics; offset compensation; process variation; random access storage; sense amplifier; SRAM chips; voltage scaling

Indexed keywords

CMOS MEMORY CIRCUITS; OFFSET COMPENSATION; PROCESS VARIATION; SENSE AMPLIFIER; SRAM CHIP; VOLTAGE-SCALING;

AMPLIFIERS (ELECTRONIC); CACHE MEMORY; LEAKAGE CURRENTS; POWER ELECTRONICS; SENSORS;

STATIC RANDOM ACCESS STORAGE;

EID: 78650885828     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2085970     Document Type: Conference Paper

References (24)

1. D. J. Frank, W. Haensch, G. Shahidi, and H. Dokumaci, "Optimizing CMOS technology for maximum performance," IBM J. Res. Dev., vol. 50, no. 4/5, p. 419, Jul./Sep. 2006.
2. R. K. Krishnamurthy, A. Alvandpour, S. Mathew, M. Anders, V. De, and S. Borkar, "High-performance, low-power, and leakage-tolerance challenges for sub-70 nm microprocessor circuits," in Proc. Eur. Solid State Circuits Conf. (ESSCIRC), 2002, pp. 315-321.
3. L. Chang, R. K. Montoye, Y. Nakamura, K. A. Batson, R. J. Eickemeyer, R. H. Dennard, W. Haensch, and D. Jamsek, "An 8t-sram for variability tolerance and low-voltage operation in high-performance caches," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 956-963, 2008.
4. A. Alvandpour, R. K. Krishnamurthy, K. Soumyanath, and S. Y. Borkar, "A sub-130-nm conditional keeper technique," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 633-638, 2002.
5. I. Arsovski and R.Wistort, "Self-referenced sense amplifier for acrosschip- variation immune sensing in high-performance content-addressable memories," in Proc. IEEE Custom Integrated Circuits Conf., 2006, pp. 453-456.
6. N. Verma and A. P. Chandrakasan, "A high-density 45 nm SRAM using small-signal non-strobed regenerative sensing," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp. 380-621.
7. A. Singh, M. Ciraula, D. Weiss, J. Wuu, P. Bauser, P. de Champs, H. Daghighian, D. Fisch, P. Graber, and M. Bron, "A 2 ns-read-latency 4 Mb embedded floating-body memory macro in 45 nm SoI technology," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2009, pp. 460-461.
8. K. Zhang, U. Bhattacharya, L. Ma, Y. Ng, B. Zheng, M. Bohr, and S. Thompson, "A fully synchronized, pipelined, and re-configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications," in Symp. VLSI Circuits Dig., 2003, pp. 253-254.
9. K. Zhang, K. Hose, V. De, and B. Senyk, "The scaling of data sensing schemes for high speed cache design in sub-0.18 μm technologies," in IEEE Symp. VLSI Circuits Dig., 2000, pp. 226-227.
10. H. Pilo, V. Ramadurai, G. Braceras, J. Gabric, S. Lamphier, and Y. Tan, "A 450 ps access-time SRAM macro in 45 nm SOI featuring a two-stage sensing-scheme and dynamic power management," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp. 378-621.
11. H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, "Sram leakage suppression by minimizing standby supply voltage," in Proc. Int. Symp. Quality Electronic Design, 2004, pp. 55-60.
12. K. Nii, Y. Tenoh, T. Yoshizawa, S. Imaoka, Y. Tsukamoto, Y. Yamagami, T. Suzuki, A. Shibayama, H. Makino, and S. Iwade, "A 90 nm low power 32 k-byte embedded SRAM with gate leakage suppression circuit for mobile applications," in IEEE Symp. VLSI Circuits Dig., 2003, pp. 247-250.
13. M. Yamaoka, Y. Shinozaki, N. Maeda, Y. Shimazaki, K. Kato, S. Shimada, K. Yanagisawa, and K. Osadal, "A 300 MHz 25μA/Mb leakage on-chip SRAM module featuring process-variation immunity and lowleakage- active mode for mobile-phone application processor," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2004, pp. 494-542.
14. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, "Sram design on 65 nm CMOS technology with integrated leakage reduction scheme," in IEEE Symp. VLSI Circuits Dig., 2004, pp. 294-295.
15. F. Hamzaoglu, K. Zhang, Y. Wang, H. J. Ann, U. Bhattacharya, Z. Chen, Y. Ng, A. Pavlov, K. Smits, and M. Bohr, "A 153 mb-sram design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal-gate CMOS technology," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp. 376-621.
16. Y. Takeyama, H. Otake, O. Hirabayashi, K.Kushida, and N. Otsuka, "A low leakage SRAM macro with replica cell biasing scheme," in IEEE Symp. VLSI Circuits Dig., 2005, pp. 166-167.
17. J. Wang and B. H. Calhouns, "Canary replica feedback for near-DRV standby Vdd scaling in a 90 nm SRAM," in Proc. IEEE Custom Integrated Circuits Conf., 2007, pp. 29-32.
18. A. Singhee and R. A. Rutenbar, "Statistical blockade: A novel method for very fast monte carlo simulation of rare circuit events, and its application," in DATE 2007.
19. R. Kanj, R. Joshi, and S. Nassif, "Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events," in Design Automation Conf., San Francisco, CA, 2006, pp. 69-72, ACM.
20. L. Dolecek, M. Qazi, D. Shah, and A. Chandrakasan, "Breaking the simulation barrier: SRAM evaluation through norm minimization," in IEEE/ACM Int. Conf. Computer-Aided Design, 2008, pp. 322-329.
21. M. Qazi, M. Tikekar, L. Dolecek, D. Shah, and A. P. Chandrakasan, "Loop flattening and spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis," in Design Automation & Test in Europe, Mar. 2010, pp. 801-806.
22. K. J. Antreich and H. E. Graeb, "Circuit optimization driven by worst-case distances," in IEEE/ACM Int. Conf. Computer-Aided Design, 1991, pp. 166-169.
23. X. Deng, W. K. Loh, B. Pious, T. W. Houston, L. Liu, B. Khan, and D. Corum, "Characterization of bit transistors in a functional sram," in IEEE Symp. VLSI Circuits Dig., 2008, pp. 44-45.
24. Y. Wang, U. Bhattacharya, F. Hamzaoglu, P. Kolar, Y. Ng, L. Wei, Y. Zhang, K. Zhang, and M. Bohr, "A 4.0 GHz 291Mb voltage-scalable SRAM design in 32 nm high-k metal-gate CMOS with integrated power management," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2009.