5T SRAM with asymmetric sizing for improved read stability

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 10, 2011, Pages 2431-2442

  Nalam, Satyanand ^a   Calhoun, Benton H ^a  

^a University of Virginia   (United States)

Author keywords

95T SRAM; Asymmetric sizing; single ended bitcell; static noise margin

Indexed keywords

5T SRAM; ASYMMETRIC SIZING; BITCELL; GLOBAL VARIATIONS; MEASUREMENT RESULTS; READ STABILITY; SINGLE-ENDED; SRAM DESIGN; STATIC NOISE MARGIN; SUPPLY VOLTAGES; TEST CHIPS;

LOGIC DESIGN;

EID: 80053637661     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2160812     Document Type: Conference Paper

References (36)

1. A. Bhavnagarwala, X. Tang, and J. Meindl, "The impact of intrinsic device fluctuations onCMOS SRAM cell stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001.
2. L. Chang, Y. Nakamura, R. Montoye, J. Sawada, A. Martin, K. Kinoshita, F. Gebara, K. Agarwal, D. Acharyya, W. Haensch, K. Hosokawa, and D. Jamsek, "A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65 nm CMOS," in 2007 IEEE Symp. VLSI Circuits Dig., Jun. 2007, pp. 252-253.
3. R. Kumar and G. Hinton, "A family of 45 nm IA processors," in 2009 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 58-59.
4. D.Wendel, R. Kalla, R. Cargoni, J. Clables, J. Friedrich, R. Frech, J. Kahle, B. Sinharoy, W. Starke, S. Taylor, S.Weitzel, S. Chu, S. Islam, and V. Zyuban, "The implementation of Power7(tm): A highly parallel and scalable multi-core high-end server processor," in 2010 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2010, pp. 102-103.
5. R. Jotwani, S. Sundaram, S. Kosonocky, A. Schaefer, V. Andrade, G. Constant, A. Novak, and S. Naffziger, "An x86-64 core implemented in 32 nm SOI CMOS," in 2010 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2010, pp. 106-107.
6. J. Pille, D. Wendel, O. Wagner, R. Sautter, W. Penth, T. Froehnel, S. Buettner, O. Torreiter, M. Eckert, J. Paredes, D. Hrusecky, D. Ray, and M. Canada, "A 32kb 2r/1w l1 data cache in 45nm SOI technology for the Power7(tm) processor," in 2010 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2010, pp. 344-345.
7. A. Bhavnagarwala, S.Kosonocky, C. Radens,Y. Chan, K. Stawiasz, U. Srinivasan, S. Kowalczyk, andM. Ziegler, "A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 946-955, Apr. 2008.
8. S. Ohbayashi, M.Yabuuchi,K.Nii,Y. Tsukamoto, S. Imaoka, Y.Oda, T. Yoshihara, M. Igarashi,M. Takeuchi, H. Kawashima,Y. Yamaguchi, K. Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi, and H. Shinohara, "A 65-nm SOC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 820-829, Apr. 2007.
9. M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, "Low-power embedded SRAM modules with expanded margins for writing," in 2005 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, vol. 1, pp. 480-611.
10. Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, "An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment," in 2007 IEEE Symp. VLSI Circuits Dig., Jun. 2007, pp. 256-257.
11. S. Nalam and B. Calhoun, "Asymmetric sizing in a 45 nm 5T SRAM to improve read stability over 6T," in Proc. 2009 IEEE Custom Integrated Circuits Conf. (CICC), 2009, pp. 709-712.
12. I. Carlson, S. Andersson, S. Natarajan, and A. Alvandpour, "A high density, low leakage, 5T SRAM for embedded caches," in Proc. 30th European Solid-State Circuits Conf. (ESSCIRC), Sep. 2004, pp. 215-218.
13. M.Wieckowski andM.Margala, "A portless SRAM cell using stunted wordline drivers," in Proc. 2008 IEEE Int. Symp. Circuits and Systems (ISCAS), May 2008, pp. 584-587.
14. A. Kawasumi, T. Yabe, Y. Takeyama, O. Hirabayashi, K. Kushida, A. Tohata, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, and N. Otsuka, "A single-power-supply 0.7 V 1 GHz 45 nm SRAM with an asymmetrical unit-Ratio memory cell," in 2008 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, pp. 382-622.
15. E. Seevinck, F. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. 22, no. 10, pp. 748-754, Oct. 1987.
16. A. Srivastava, "Simultaneous Vt selection and assignment for leakage optimization," in Proc. 2003 IEEE Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2003, pp. 146-151.
17. S. Borkar, "Design challenges for 22 nm CMOS and beyond," in 2009 IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., Dec. 2009, p. 1.
18. S. Nalam, V. Chandra, C. Pietrzyk, R. Aitken, and B. Calhoun, "Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation," in Proc. 11th Int. Symp. Quality Electronic Design (ISQED), Mar. 2010, pp. 139-146.
19. M. Khellah, N. S. Kim, Y. Ye, D. Somasekhar, T. Karnik, N. Borkar, G. Pandya, F. Hamzaoglu, T. Coan, Y.Wang, K. Zhang, C.Webb, and V. De, "Process, temperature, and supply-noise tolerant 45 nm dense cache arrays with diffusion-notch-free (DNF) 6T SRAM cells and dynamic multi-Vcc circuits," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1199-1208, Apr. 2009.
20. H. Pilo, J. Barwin, G. Braceras, C. Browning, S. Burns, J. Gabric, S. Lamphier, M. Miller, A. Roberts, and F. Towler, "An SRAM design in 65nm and 45nm technology nodes featuring read and write-assist circuits to expand operating voltage," in 2006 Symp. VLSI Circuits Dig. Tech. Papers, 2006, pp. 15-16.
21. Y. Morita, H. Fujiwara, H. Noguchi, K. Kawakami, J. Miyakoshi, S. Mikami, K. Nii, H. Kawaguchi, and M. Yoshimoto, "A Vth-variationtolerant SRAM with 0.3-V minimum operation voltage for memoryrich SOC under DVS environment," in 2006 Symp. VLSI Circuits Dig. Tech. Papers, 2006, pp. 13-14.
22. 2 cell in 40 nm CMOS using level-programmable wordline driver," in 2009 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 458-459, 459a.
23. B. Mohammad, M. Saint-Laurent, P. Bassett, and J. Abraham, "Cache design for low power and high yield," in Proc. 9th Int. Symp. Quality Electronic Design (ISQED), 2008, pp. 103-107.
24. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, "A 3-GHz 70-MB SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 146-151, Jan. 2006.
25. Y. H. Chen, G. Chan, S. Y. Chou, H.-Y. Pan, J.-J.Wu, R. Lee, H. Liao, and H. Yamauchi, "A 0.6 V dual-rail compiler SRAM design on 45 nm CMOS technology with adaptive SRAM power for lower Vdd-min VLSIs," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1209-1215, Apr. 2009.
26. M. Iijima, K. Seto, M. Numa, A. Tada, and T. Ipposhi, "Low power SRAM with boost driver generating pulsed word line voltage for sub-1V operation," J. Computers, vol. 3, no. 5, 2008.
27. Y. Chung and S.-H. Song, "Implementation of low-voltage static RAM with enhanced data stability and circuit speed," Microelectron. J., vol. 40, pp. 944-951, Jun. 2009.
28. R. W. Mann, J. Wang, S. Nalam, S. Khanna, G. Braceras, H. Pilo, and B. H. Calhoun, "Impact of circuit assist methods on margin and performance in 6T SRAM," Solid-State Electronics, vol. 54, no. 11, pp. 1398-1407, 2010.
29. B. Calhoun and A. Chandrakasan, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1673-1679, Jul. 2006.
30. Y. Ye, M. Khellah, D. Somasekhar, and V. De, "Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches," in Proc. 2006 IEEE Int. Symp. Circuits and Systems (ISCAS), 2006, pp. 4-966.
31. N. Gierczynski, B. Borot, N. Planes, and H. Brut, "A new combined methodology for write-margin extraction of advanced sram," in Proc. IEEE Int. Conf. Microelectronic Test Structures (ICMTS'07), Mar. 2007, pp. 97-100.
32. N. Tzartzanis and W. Walker, "A differential current-mode sensing method for high-noise-immunity, single-ended register files," in 2004 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004, vol. 1, pp. 506-543.
33. J. Poulton, "An embedded DRAM for CMOS ASICs," in Proc. 17th Conf. Advanced Research in VLSI, Sep. 1997, pp. 288-302.
34. N. Verma and A. Chandrakasan, "A high-density 45 nm SRAM using small-signal non-strobed regenerative sensing," in 2008 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, pp. 380-621.
35. J. Yeung and H. Mahmoodi, "Robust sense amplifier design under random dopant fluctuations in nano-scale CMOS technologies," in Proc. IEEE Int. SOC Conf. 2006, Sep. 2006, pp. 261-264.
36. J.Wang, S. Nalam, and B. H. Calhoun, "Analyzing static and dynamic write margin for nanometer SRAMs," in Proc. 13th Int. Symp. Low Power Electronics and Design (ISLPED), New York, 2008, pp. 129-134.