Design and analysis of A 5.3-pJ 64-kb gated ground SRAM with multiword ECC

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 9, 2009, Pages 2543-2553

  Jahinuzzaman, Shah M ^a   Shah, Jaspal Singh ^b   Rennie, David J ^b   Sachdev, Manoj ^b  

^a Dept of Electrical and Computer Engineering   (Canada)

^b UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Error correction; Leakage current; Multiword; Soft error; SRAM chips

Indexed keywords

90NM CMOS; BIT ENERGY; CRITICAL CHARGE; DATA LATENCIES; DESIGN AND ANALYSIS; ECC SCHEME; GROUND POTENTIAL; LEAKAGE POWER CONSUMPTION; LEAKAGE REDUCTION; MULTI-BIT ERROR; MULTIWORD; NEUTRON RADIATIONS; NONZERO VALUES; SOFT ERROR; SOFT ERROR RATE; SPEED IMPROVEMENT; SRAM CHIPS; SRAM MACRO; WRITE OPERATIONS;

CMOS INTEGRATED CIRCUITS; COSMOLOGY; ENERGY CONSERVATION; LEAKAGE CURRENTS; STATIC RANDOM ACCESS STORAGE;

ERROR CORRECTION;

EID: 70249128051     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2021088     Document Type: Article

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