A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 1, 2008, Pages 141-149

  Verma, Naveen ^a   Chandrakasan, Anantha P ^a  

^a Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

Cache memories; CMOS memory circuits; leakage currents; low power electronics; redundancy; SRAM chips

Indexed keywords

EID: 85008054031     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.2007.908005     Document Type: Article

References (17)

1. A. Wang, A. Chandrakasan, and S. Kosonocky, “Optimal suppply and threshold scaling for subthreshold CMOS circuits,” in Proc. IEEE Comput. Soc. Annu. Int. Symp. VLSI, Apr. 2002, pp. 5–9.
2. t SRAM employing sense-amplifier redundancy,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 328–329.
3. B. Calhoun and A. Chandrakasan, “A 256 kb subthreshold SRAM in 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 480–481.
4. J. Chen, L. Clark, and T.-H. Chen, “An ultra-low-power memory with a subthreshold power supply voltage,” IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2344–2353, Oct. 2006.
5. A. Wang and A. Chandrakasan, “A 180 mV FFT processor using subthreshold circuit techniques,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2004, pp. 292–293.
6. T. Mizumo, J.-I. Okamura, and A. Toriumi, “Experimental study of threshold voltage fluctuations using an 8 k MOSFET's array,” in Proc. IEEE Symp. VLSI Technology, May 1993, pp. 41–42.
7. S.-W. Sun and P. G. Y. Tsui, “Limitations of CMOS supply-voltage scaling by MOSFET threshold-voltage variation,” IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 947–949, Aug. 1995.
8. A. Bhavnagarwala, X. Tang, and J. Meindl, “The impact of intrinsic device fluctuations on CMOS SRAM cell stability,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658–665, Apr. 2001.
9. E. Seevinck, F. J. List, and J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells,” IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748–754, Oct. 1987.
10. L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch, “Stable SRAM cell design for the 32 nm node and beyond,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2005, pp. 128–129.
11. Y. Ye, S. Borkar, and V. De, “A new technique for standby leakage reduction in high performance circuits,” in Proc. IEEE Symp. VLSI Circuits, Jun. 1998, pp. 40–41.
12. K. Zhang, K. Hose, V. De, and B. Senyk, “The scaling of data sensing schemes for high speed cache design in sub-0.18 μm technologies,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2000, pp. 226–227.
13. M. Pelgrom, H. Tuinhout, and M. Vertregt, “Transistor matching in analog CMOS applications,” in IEDM Dig. Tech. Papers, Dec. 1998, pp. 915–918.
14. P. Kinget, “Device mismatch and tradeoffs in the design of analog circuits,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1212–1224, Jun. 2005.
15. M. P. Flynn, C. Donovan, and L. Sattler, “Digital calibration incorporating redundancy of flash ADCs,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 3, pp. 205–213, May 2003.
16. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “A SRAM design on 65 nm CMOS technology with integrated leakage reduction scheme,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2004, pp. 294–295.
17. M. Yamaoka, N. Maeda, Y. Shinozaki, Y. S. K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, “Low power embedded SRAM modules with expanded margins for writing,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 480–481.