0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

ESSCIRC 2010 - 36th European Solid State Circuits Conference

Volumn , Issue , 2010, Pages 354-357

  Suzuki, Toshikazu ^a   Moriwaki, Shinichi ^a   Kawasumi, Atsushi ^a   Miyano, Shinji ^a   Shinohara, Hirofumi ^a  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; 8T-CELL; BIT LINES; CELL LAYOUT; CMOS TECHNOLOGY; DELAY VARIATION; HIGH-SPEED; LOW-VOLTAGE; MEMORY CELL; OPERATING FREQUENCY; POINT SYMMETRY; POWER-DELAY PRODUCTS; READ SPEED; SENSE AMPLIFIER; SIMULATED RESULTS; SMALL AREA; TEST CHIPS;

CMOS INTEGRATED CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 78650375733     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2010.5619716     Document Type: Conference Paper

References (12)

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