Technology variability from a design perspective

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 58, Issue 9, 2011, Pages 1996-2009

  Nikolić, Borivoje ^a   Park, Ji Hoon ^a   Kwak, Jaehwa ^a   Giraud, Bastien ^b   Guo, Zheng ^c   Pang, Liang Teck ^d   Toh, Seng Oon ^a   Jevtić, Ruzica ^a   Qian, Kun ^a   Spanos, Costas ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b CEA LETI   (France)

^c INTEL CORPORATION   (United States)

^d IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

CMOS; digital logic; SRAM; static timing analysis; variability

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; LOGIC DESIGN; SEMICONDUCTOR DEVICES; STATIC RANDOM ACCESS STORAGE;

DIGITAL LOGIC; OPERATING VOLTAGE; RANDOM VARIABILITY; SEMICONDUCTOR PROCESS TECHNOLOGY; STATIC TIMING ANALYSIS; TEMPORAL CHARACTERISTICS; TRANSISTOR ARRAYS; VARIABILITY;

INTEGRATED CIRCUIT DESIGN;

EID: 80052907957     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2011.2165389     Document Type: Review

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