Dynamic SRAM stability characterization in 45nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 35-36

  Toh, Seng Oon ^a   Guo, Zheng ^a   Nikolić, Borivoje ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENHANCED SENSITIVITY; NEGATIVE BIAS TEMPERATURE INSTABILITY; PROCESS VARIATION; READ MARGIN; SRAM STABILITY; WORDLINES; WRITE MARGIN;

INTEGRATED CIRCUIT TESTING; SENSITIVITY ANALYSIS; STABILITY; STATIC RANDOM ACCESS STORAGE;

VLSI CIRCUITS;

EID: 77957975231     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560259     Document Type: Conference Paper

References (6)

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3. M. Sharifkhani and M. Sachdev, IEEE JSSC, Feb., 2009.
4. R. Joshi, et al., VLSI Circ., 2007.
5. Z. Guo, et al., IEEE JSSC, Nov., 2009.
6. S. Kumar, C. Kim, and S. Sapatnekar, ISQED 2006.