Impact of layout on 90nm CMOS process parameter fluctuations

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 69-70

  Pang, Liang Teck ^a   Nikolic, Borivoje ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; DIGITAL CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; PARAMETER ESTIMATION; TRANSISTORS;

PARAMETER FLUCTUATIONS; RING OSCILLATOR FREQUENCIES;

CMOS INTEGRATED CIRCUITS;

EID: 39749152930     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J.W. Tschanz, et al., "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," IEEE Journal of Solid-State Circuits, Nov. 2002.
2. D.Boning et al., "Test Structures for Delay Variability" TAU 2002.
3. M. Orshansky, et al. "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits", IEEE Trans. CAD, May 2002