Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 11, 2002, Pages 1396-1402

  Tschanz, James W ^a   Kao, James T ^b   Narendra, Siva G ^a   Nair, Raj ^a   Antoniadis, Dimitri A ^b   Chandrakasan, Anantha P ^b   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Body bias; CMOS digital integrated circuits; Forward bias; Low power circuits; Microprocessors; Parameter variations; Substrate bias; Within die variation

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; THRESHOLD VOLTAGE;

BODY BIAS; FORWARD BIAS; LOW POWER CIRCUITS; PARAMETER VARIATIONS; SUBSTRATE BIAS;

MICROPROCESSOR CHIPS;

EID: 0036858210     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.803949     Document Type: Article

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