SRAM stability characterization using tunable ring oscillators in 45nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 354-355

  Tsai, Jason ^a   Toh, Seng Oon ^a   Guo, Zheng ^a   Pang, Liang Teck ^a,b   Liu, Tsu Jae King ^a   Nikolic, Borivoje ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL STABILITY; DATA SETS; DYNAMIC OPERATIONS; OPERATING FREQUENCY; OPERATING VOLTAGE; PERFORMANCE VARIATIONS; READ OPERATION; RING OSCILLATOR; SRAM CELL; SRAM STABILITY; STATIC NOISE MARGIN; WRITE MARGIN;

OSCILLATORS (ELECTRONIC);

STATIC RANDOM ACCESS STORAGE;

EID: 77952151798     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433820     Document Type: Conference Paper

References (5)

1. A. J. Bhavnagarwala, et al., "A Sub-600mV Fluctuation Tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 946-955, Apr. 2008.
2. Z. Guo, et al., "Large-Scale Read/Write Margin Measurement in 45nm CMOS SRAM Arrays," Symposium on VLSI Circuits, pp. 42-43, Jun. 2008.
3. G. D. Carpenter, et al., "Pulsed Ring Oscillator Circuit for Storage Cell Read Timing Evaluation," U.S. Patent No. 7,409,305, Aug. 5, 2008.
4. C. Wann, et al., "SRAM Cell Design for Stability Methodology," IEEE VLSITSA, pp. 21-22, Apr. 2005.
5. E. Grossar, et al., "Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2577-2588, Nov. 2006.