On-chip transistor characterisation arrays for variability analysis

Electronics Letters

Volumn 43, Issue 15, 2007, Pages 806-808

  Wang, V ^a   Shepard, K L ^a  

^a Department of Earth and Environmental Sciences   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; MICROPROCESSOR CHIPS; RAPID PROTOTYPING; VOLTAGE CONTROL;

CURRENT-VOLTAGE CHARACTERIZATION; PROTOTYPE MACRO;

TRANSISTORS;

EID: 34547224000     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20070017     Document Type: Article

References (6)

1. Nassif, S.: ' Delay variability: sources, impacts, and trends ', Proc. Int. Solid-State Circuits Conf., 2000, p. 368-369
2. Pelgrom, M., Duinmaijer, A.C.J., and Welbers, A.P.G.: ' Matching properties of MOS transistors ', IEEE J. Solid-State Circuits, 1989, 24, p. 1433-1440 10.1109/JSSC.1989.572629 0018-9200
3. Pang, L.-T., and Nikolic, B.: ' Impact of layout on 90nm CMOS process parameter fluctuations ', Symp. on VLSI Circuits, 2006, p. 69-70
4. Agarwal, K., Liu, F., McDowell, C., Nassif, S., Nowka, K., Palmer, M., Acharyya, D., and Plusquellie, J.: ' A test structure for characterizing local device mismatches ', Symp. VLSI Circuits, 2006, p. 67-68
5. Bananezhad, J.: ' A rail-to-rail CMOS op amp ', IEEE J. Solid-State Circuits, 1988, 23, p. 1414-1417 0018-9200
6. Mucher, M., Lallement, C., Enz, C., Theodoloz, F., and Krummenacher, F.: ' The EPFL-EKV MOSFET model equations for simulation ', http://legwww.epfl.ch/ ekv/pdf/ekv_v262.pdf