-
1
-
-
0034833288
-
Modeling and analysis of manufacturing variations
-
S. R. Nassif, "Modeling and analysis of manufacturing variations," in Proc. IEEE Conf Custom Integr. Circuits, 2001, pp. 223-228.
-
(2001)
Proc. IEEE Conf Custom Integr. Circuits
, pp. 223-228
-
-
Nassif, S.R.1
-
2
-
-
0042635808
-
Death, Taxes and failing chips
-
C. Visweswariah. "Death, Taxes and failing chips," in Proc. Des. Autom. Conf., 2003, pp. 343-347.
-
(2003)
Proc. Des. Autom. Conf
, pp. 343-347
-
-
Visweswariah, C.1
-
3
-
-
0041633858
-
Parameter variation and impact on circuits and microarchitecture
-
S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variation and impact on circuits and microarchitecture." in Proc. Des. Autom. Conf., 2003, pp. 338-342.
-
(2003)
Proc. Des. Autom. Conf
, pp. 338-342
-
-
Borkar, S.1
Karnik, T.2
Narendra, S.3
Tschanz, J.4
Keshavarzi, A.5
De, V.6
-
4
-
-
0035308547
-
The impact of intrinsic device fluctuations on CMOS SRAM cell stability
-
Apr
-
A. Bhavnagarwala, X. Tang, and J. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid-State Circuits, vol. 36. no. 4, pp. 658-665, Apr. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.4
, pp. 658-665
-
-
Bhavnagarwala, A.1
Tang, X.2
Meindl, J.3
-
5
-
-
0031365880
-
Intrinsic MOSFET parameter fluctuations due to random dopant placement
-
Dec
-
X. Tang. V. De, and J. Meindl, "Intrinsic MOSFET parameter fluctuations due to random dopant placement," IEEE Trans. Very Large Scale Integr. Syst., vol. 5, no. 4, pp. 369-376, Dec. 1997.
-
(1997)
IEEE Trans. Very Large Scale Integr. Syst
, vol.5
, Issue.4
, pp. 369-376
-
-
Tang, X.1
De, V.2
Meindl, J.3
-
6
-
-
0016572578
-
The effect of randomness in the distribution of impurity atoms on FET threshold
-
R. W. Keyes, "The effect of randomness in the distribution of impurity atoms on FET threshold," J. Appl. Phys. A: Mater. Sci. Process., vol. 8, pp. 251-259, 1975.
-
(1975)
J. Appl. Phys. A: Mater. Sci. Process
, vol.8
, pp. 251-259
-
-
Keyes, R.W.1
-
7
-
-
85001841209
-
Experimental study of threshold voltage fluctuations using an 8 K MOSFET array
-
T. Mizuno, J. Okamura, and A. Toriumi, "Experimental study of threshold voltage fluctuations using an 8 K MOSFET array," in Proc. Symp. VLSI Technol., 1993, pp. 41-42.
-
(1993)
Proc. Symp. VLSI Technol
, pp. 41-42
-
-
Mizuno, T.1
Okamura, J.2
Toriumi, A.3
-
9
-
-
0028571338
-
Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits
-
D. Burnett, K. Erington, C. Subramanian, and K. Baker, "Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits," in Proc. Symp. VLSI Technol., 1994. pp. 15-16.
-
(1994)
Proc. Symp. VLSI Technol
, pp. 15-16
-
-
Burnett, D.1
Erington, K.2
Subramanian, C.3
Baker, K.4
-
10
-
-
33846061871
-
Erratic fluctuations of SRAM cache Vmin at the 90 nm process technology node
-
M. Agostinelli et al., "Erratic fluctuations of SRAM cache Vmin at the 90 nm process technology node," in Proc. IEEE Int. Electron Device Meet., 2005. pp. 655-658.
-
(2005)
Proc. IEEE Int. Electron Device Meet
, pp. 655-658
-
-
Agostinelli, M.1
-
11
-
-
0023437909
-
Static-noise margin analysis of MOS SRAM cells
-
Oct
-
E. Seevinck, F. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. SC-22, no. 10, pp. 748-754, Oct. 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.SC-22
, Issue.10
, pp. 748-754
-
-
Seevinck, E.1
List, F.2
Lohstroh, J.3
-
12
-
-
33847721007
-
Fluctuation limits & scaling opportunities for CMOS SRAM cells
-
A. Bhavnagarwala, S. Kosonocky, C. Radens, K. Stawiasz, R. Mann, Q. Ye. and K. Chin, "Fluctuation limits & scaling opportunities for CMOS SRAM cells," in Proc. IEEE Int. Electron Device Meet., 2005, pp. 659-662.
-
(2005)
Proc. IEEE Int. Electron Device Meet
, pp. 659-662
-
-
Bhavnagarwala, A.1
Kosonocky, S.2
Radens, C.3
Stawiasz, K.4
Mann, R.5
Ye, Q.6
Chin, K.7
-
13
-
-
28144454581
-
A 3 GHz 70 Mb SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply
-
K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, "A 3 GHz 70 Mb SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply," in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 474-475.
-
(2005)
Proc. IEEE Int. Solid-State Circuits Conf
, pp. 474-475
-
-
Zhang, K.1
Bhattacharya, U.2
Chen, Z.3
Hamzaoglu, F.4
Murray, D.5
Vallepalli, N.6
Wang, Y.7
Zheng, B.8
Bohr, M.9
-
14
-
-
33846259499
-
Wordline & bitline pulsing schemes for improving SRAM cell stability in low-vcc 65 nm CMOS designs
-
M. Khellah, Y. Ye, N. S. Kim, D. Somasekhar, G. Pandya, A. Farhang, K. Zhang, C. Webb, and V. De, "Wordline & bitline pulsing schemes for improving SRAM cell stability in low-vcc 65 nm CMOS designs," in Proc. Symp. VLSI Circuits, 2006, pp. 9-10.
-
(2006)
Proc. Symp. VLSI Circuits
, pp. 9-10
-
-
Khellah, M.1
Ye, Y.2
Kim, N.S.3
Somasekhar, D.4
Pandya, G.5
Farhang, A.6
Zhang, K.7
Webb, C.8
De, V.9
-
15
-
-
39749201604
-
An SRAM design in 65 nm and 45 nm technology nodes featuring read and write-assist circuits to expand operating voltage
-
H. Pilo, J. Barwin, G. Braceras, C. Browning, S. Burns, J. Gabric, S. Lamphier, M. Miller. A. Roberts, and F. Towler, "An SRAM design in 65 nm and 45 nm technology nodes featuring read and write-assist circuits to expand operating voltage," in Proc. Symp. VLSI Circuits, 2006, pp. 15-16.
-
(2006)
Proc. Symp. VLSI Circuits
, pp. 15-16
-
-
Pilo, H.1
Barwin, J.2
Braceras, G.3
Browning, C.4
Burns, S.5
Gabric, J.6
Lamphier, S.7
Miller, M.8
Roberts, A.9
Towler, F.10
-
16
-
-
0002643538
-
Use of different Monte Carlo sampling techniques
-
H. Kahn, "Use of different Monte Carlo sampling techniques," in Proc. Symp. Monte Carlo Methods, 1956, pp. 149-190.
-
(1956)
Proc. Symp. Monte Carlo Methods
, pp. 149-190
-
-
Kahn, H.1
-
18
-
-
56749085035
-
Introduction to statistical variation and techniques for design optimization
-
Feb
-
N. Rohrer, "Introduction to statistical variation and techniques for design optimization," in Proc. IEEE Int. Solid-State Circuits Conf. Tutorial, Feb. 2006, pp. 1-92.
-
(2006)
Proc. IEEE Int. Solid-State Circuits Conf. Tutorial
, pp. 1-92
-
-
Rohrer, N.1
-
19
-
-
0016026184
-
Exact and invariant second-moment code format
-
Jan
-
A. M. Hasofer and N. C. Lind, "Exact and invariant second-moment code format," J. ASCE Eng. Mechanics Div., vol. 100, no. 1, pp. 111-121, Jan. 1974.
-
(1974)
J. ASCE Eng. Mechanics Div
, vol.100
, Issue.1
, pp. 111-121
-
-
Hasofer, A.M.1
Lind, N.C.2
-
20
-
-
84908051251
-
Methods for efficient probabilistic analysis of system with large numbers of random variables
-
presented at the, St. Louis, MO, AIAA-1998-4908
-
Y. T. Wu, "Methods for efficient probabilistic analysis of system with large numbers of random variables," presented at the AIAA/USAF/NASA/ISSMO Symp. Multidisciplinary Anal. Optimization. St. Louis, MO, 1998, AIAA-1998-4908.
-
(1998)
AIAA/USAF/NASA/ISSMO Symp. Multidisciplinary Anal. Optimization
-
-
Wu, Y.T.1
-
21
-
-
0025488619
-
Advanced probabilistic structural analysis method for implicit performance functions
-
Y. T. Wu, H. R. Millwater, and T. A. Cruse, "Advanced probabilistic structural analysis method for implicit performance functions," AIAA J., vol. 28, no. 9, pp. 1663-1669, 1990.
-
(1990)
AIAA J
, vol.28
, Issue.9
, pp. 1663-1669
-
-
Wu, Y.T.1
Millwater, H.R.2
Cruse, T.A.3
-
24
-
-
0002872544
-
A most probable point-based method for efficient uncertainty analysis
-
Oct
-
X. Du and W. Chen, "A most probable point-based method for efficient uncertainty analysis," J. Des. Manufacturing Autom., vol. 4, no. 1, pp. 47-66, Oct. 2001.
-
(2001)
J. Des. Manufacturing Autom
, vol.4
, Issue.1
, pp. 47-66
-
-
Du, X.1
Chen, W.2
-
25
-
-
29144526605
-
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
-
Dec
-
S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 12, pp. 1859-1880, Dec. 2005.
-
(2005)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst
, vol.24
, Issue.12
, pp. 1859-1880
-
-
Mukhopadhyay, S.1
Mahmoodi, H.2
Roy, K.3
-
26
-
-
39749107272
-
Effect of power supply noise on SRAM dynamic stability
-
M. Khellah, D. Khalil, D. Somasekhar, Y. Ismail, T. Karnik, and V. De, "Effect of power supply noise on SRAM dynamic stability," in Proc. Symp. VLSI Circuits, 2007, pp. 76-77.
-
(2007)
Proc. Symp. VLSI Circuits
, pp. 76-77
-
-
Khellah, M.1
Khalil, D.2
Somasekhar, D.3
Ismail, Y.4
Karnik, T.5
De, V.6
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