Measurement and analysis of variability in 45 nm strained-Si CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 8, 2009, Pages 2233-2243

  Pang, Liang Teck ^a,b   Qian, Kun ^a   Spanos, Costas J ^a   Nikolic, Borivoje ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

45 nm; CMOS; Layout; Leakage; Ring oscillators; Strain; Variability

Indexed keywords

45 NM; CMOS; LAYOUT; LEAKAGE; RING OSCILLATORS; VARIABILITY;

CMOS INTEGRATED CIRCUITS; DIES; SILICON WAFERS;

OSCILLATORS (ELECTRONIC);

EID: 68549087134     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2022217     Document Type: Article

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