Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for Gigascale integration

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 2, 2002, Pages 183-190

  Bowman, Keith A ^a,b,c   Duvall, Steven G ^a,c,d   Meindl, James D ^a,b  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c INTEL CORPORATION   (United States)

^d Intel Australia Pty Ltd   (Australia)

Author keywords

Critical path delay variations; Die to die and within die fluctuations; FMAX distribution; Gate delay variations; Inter die and intra die fluctuations; Manufacturing tolerances; Maximum clock frequency distribution; Parameter variations; Technology projections

Indexed keywords

MAXIMUM CLOCK FREQUENCY;

FREQUENCIES; MICROPROCESSOR CHIPS; TECHNOLOGICAL FORECASTING; TRANSISTORS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036474722     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.982424     Document Type: Article

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