All-digital circuits for measurement of spatial variation in digital circuits

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 3, 2010, Pages 640-651

  Drego, Nigel ^a   Chandrakasan, Anantha ^a   Boning, Duane ^a  

^a Department of Electrical Engineering and Computer Science   (United States)

Author keywords

Delay measurement; Digital circuits; Spatial correlation; Variation

Indexed keywords

90NM CMOS; CIRCUIT DESIGNERS; CIRCUIT STRUCTURES; CMOS PROCESSS; DELAY MEASUREMENT; DELAY MEASUREMENTS; DESIGN TOOL; DIGITAL MEASUREMENT; EXTENDED ANALYSIS; KOGGE-STONE ADDER; LAYOUT PATTERNS; LOW-VOLTAGE; MEASUREMENT DATA; PICOSECOND RESOLUTION; POWER SUPPLY VOLTAGE; RING OSCILLATOR; SPATIAL CORRELATIONS; SPATIAL VARIATIONS; SYSTEMATIC EFFECTS; TEST-CHIP; VARIATION MODELS; WITHIN-DIE VARIATIONS;

COMPUTER CRIME; DELAY CIRCUITS; DIES; DIGITAL INTEGRATED CIRCUITS; OSCILLATORS (ELECTRONIC);

ELECTRIC NETWORK ANALYSIS;

EID: 77649148729     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2039270     Document Type: Article

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