A test circuit for measurement of clocked storage element characteristics

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 8, 2004, Pages 1294-1304

  Nedovic, Nikola ^a   Walker, William W ^a   Oklobdzija, Vojin G ^b  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Clocked storage elements; Delay; Measurement circuit; Measurement error; On chip measurement; Power consumption

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; EQUIPMENT TESTING; ERROR ANALYSIS; FLIP FLOP CIRCUITS; MEASUREMENT ERRORS; RANDOM ERRORS; ROUTERS; SWITCHING CIRCUITS; TIMING CIRCUITS; VLSI CIRCUITS;

CLOCKED STORAGE ELEMENTS; DELAYS; MEASUREMENT CIRCUITS; ON-CHIP MEASUREMENT; POWER CONSUMPTIONS;

ELECTRIC CLOCKS;

EID: 3843087304     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.831498     Document Type: Article

References (13)

1. P. Hofstee et al., "A 1-GHz single-issue 64b PowerPC processor," in IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp. 92-93.
2. A. Jain et al., "A 1.2 GHz alpha microprocessor with 44.8 GB/s chip pin bandwidth," in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 240-241.
3. R. Heald et al., "A third generation SPARC V9 microprocessor," IEEE J. Solid-State Circuits, vol. 35, pp. 1526-1538, Nov. 2000.
4. S. H. Unger and C. J. Tan, "Clocking schemes for high-speed digital systems," IEEE Trans. Computers, vol. C-35, pp. 880-895, Oct. 1986.
5. V. Stojanovic and V. G. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, pp. 536-548, Apr. 1999.
6. G. Oklobdzija et al., Digital System Clocking: High-Performance and Low-Power Aspects. New York: Wiley, 2003.
7. J. U. Horstmann, H. W. Eichel, and R. L. Coates, "Metastability behavior of CMOS ASIC flip-flops in theory and test," IEEE J. Solid-State Circuits, vol. 24, pp. 146-157, Feb. 1989.
8. Q. Huang and R. Rogenmoser, "Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks," IEEE J. Solid-State Circuits, vol. 31, pp. 456-465, Mar. 1996.
9. T. Maeda et al., "An ultra-low-power-consumption high-speed GaAs quasidifferential switch flip-flop (QD-FF)," IEEE J. Solid-State Circuits, vol. 31, pp. 1361-1363, Sept. 1996.
10. B. Nikolic et al., "Improved sense-amplifier-based flip-flop: Design and measurements," IEEE J. Solid-State Circuits, vol. 35, pp. 876-884, June 2000.
11. H. D. Young, Statistical Treatment of Experimental Data. New York: McGraw-Hill, 1962.
12. V. G. Oklobdzija and V. Stojanovic, "Flip-flop," U.S. Patent 6,232,810, May 15, 2001.
13. Y. Takao et al., "A 0.11 μm CMOS technology with copper and very-low-k interconnects for high-performance system-on-a-chip cores," in IEDM Tech. Dig., Dec. 2000, pp. 559-562.