Analysis of the relationship between random telegraph signal and negative bias temperature instability

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2010, Pages 1117-1121

  Tsukamoto, Yasumasa ^a,b   Toh, Seng Oon ^b   Shin, Changhwan ^b   Mairena, Andrew ^b   Liu, Tsu Jae King ^b   Nikolić, Borivoje ^b  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Component; Hole traps; Negative bias temperature instability; Random telegraph signal; SRAM

Indexed keywords

3-DIMENSIONAL; ACCELERATION FACTORS; BIAS TEMPERATURE INSTABILITY; COMPONENT; DESIGN MARGIN; DEVICE SIMULATIONS; GATE VOLTAGES; MOS-FET; NEGATIVE BIAS TEMPERATURE INSTABILITY; PMOS TRANSISTORS; RANDOM TELEGRAPH SIGNALS; SRAM;

BIAS VOLTAGE; DEGRADATION; DESIGN; HOLE TRAPS; NEGATIVE TEMPERATURE COEFFICIENT; TELEGRAPH; THERMODYNAMIC STABILITY;

STATIC RANDOM ACCESS STORAGE;

EID: 77957891380     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2010.5488663     Document Type: Conference Paper

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