Testing the temperature limits of GaN-based HEMT devices

IEEE Transactions on Device and Materials Reliability

Volumn 10, Issue 4, 2010, Pages 427-436

  Maier, David ^a   Alomari, Mohammed ^a   Grandjean, Nicolas ^b   Carlin, Jean Francois ^b   Diforte Poisson, Marie Antoinette ^c   Dua, Christian ^c   Chuvilin, Andrey ^d   Troadec, David ^e   Gaquière, Christophe ^e   Kaiser, Ute ^d   Delage, Sylvain L ^c   Kohn, Erhard ^a  

^a UNIVERSITY OF ULM   (Germany)

^b EPFL   (Switzerland)

^c ALCATEL THALES III V LAB   (France)

^d CIC NANOGUNE   (Spain)

^e INSTITUT D ELECTRONIQUE   (France)

Author keywords

GaN heterostructures; high temperature electronics; InAlN GaN high electron mobility transistor (HEMT); reliability

Indexed keywords

ALGAN/GAN; CONTACT METALLIZATION; HETEROSTRUCTURES; HIGH TEMPERATURE STABILITY; HIGH-TEMPERATURE ELECTRONICS; IN-VACUUM; INALN/GAN HETEROSTRUCTURE; INALN/GAN HIGH-ELECTRON MOBILITY TRANSISTOR (HEMT); LARGE-SIGNALS; LATTICE-MATCHED; OPERATING TEMPERATURE; TEMPERATURE LIMITS; TEMPERATURE TEST;

CRYSTALS; ELECTRON MOBILITY; FIELD EFFECT TRANSISTORS; GALLIUM ALLOYS; GALLIUM NITRIDE; HETEROJUNCTIONS; TEMPERATURE;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 79551527678     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2010.2072507     Document Type: Article

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