Digital computation in subthreshold region for ultralow-power operation: A device-circuit-architecture codesign perspective

Proceedings of the IEEE

Volumn 98, Issue 2, 2010, Pages 160-190

  Gupta, Sumeet Kumar ^a   Raychowdhury, Arijit ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Adaptive beta ratio modulation; Double gate MOSFETs; Low voltage design; Parallelization and pipelining; Parameter variations; SRAM; Steep devices; Subthreshold logic

Indexed keywords

COMPUTATION THEORY; ELECTRIC LOSSES; ENERGY GAP; LEAKAGE CURRENTS; MOSFET DEVICES; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE; TIMING CIRCUITS;

BETA RATIO; DOUBLE-GATE MOSFETS; LOW VOLTAGE DESIGN; PARALLELIZATIONS; PARAMETER VARIATIONS; STEEP DEVICES; SUBTHRESHOLD LOGIC;

COMPUTER CIRCUITS;

EID: 75649123791     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2009.2035060     Document Type: Article

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