Double gate-MOSFET subthreshold circuit for ultralow power applications

IEEE Transactions on Electron Devices

Volumn 51, Issue 9, 2004, Pages 1468-1474

  Kim, Jae Joon ^a   Roy, Kaushik ^a  

^a IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE GATE MOSFET; GATE CAPACITANCE; PARASITIC RESISTANCE; SUBTHRESHOLD DIGITAL CIRCUIT OPERATIONS; SUBTHRESHOLD SLOPE; ULTRALOW POWER CONSUMPTION;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; OPTIMIZATION; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY;

MOSFET DEVICES;

EID: 4444275443     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.833965     Document Type: Article

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