Dynamic VTH scaling scheme for active leakage power reduction

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 163-167

  Kim, C H ^a   Roy, K ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE LEAKAGE; BODY BIAS CONTROL; CLOCK FREQUENCY; FEED-BACK LOOP; FUTURE TECHNOLOGIES; LEAKAGE POWER; SCALING SCHEMES; SUPPLY VOLTAGES;

EXHIBITIONS; VOLTAGE STABILIZING CIRCUITS;

LEAKAGE CURRENTS;

EID: 84893738755     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998265     Document Type: Conference Paper

References (8)

1. P. Macken et al, "A Voltage Reduction Technique for Digital Systems", International Solid-State Circuit Conference, Feb. 1990, pp. 238-239
2. T. D. Burd et al, "A Dynamic Voltage Scaled Microprocessor System", IEEE Journal of Solid-State Circuits, vol. 35, no. 11, Nov. 2000, pp. 1571-1580
3. G. Wei and M. Horowitz, "A Fully Digital, Energy-Efficient Adaptive Power-Supply Regulator", IEEE Journal of Solid-State Circuits, vol. 34, no. 4, Apr. 1999, pp. 520-528
4. http://www-device.eecs.berkeley.edu/~ptm/
5. K. Nose et al, "Vth-hopping Scheme for 82% Power Saving in Low-voltage Processors", Proceedings of IEEE Custom Integrated Circuits Conference, May 2001, pp. 93-96
6. T. Kuroda et al, "A 0.9-V 150-MHz, 10-mW, 4mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme", IEEE Journal of Solid-State Circuits, vol. 31, no. 11, Nov. 1996, pp. 1770-1779
7. K. Usami and M. Horowitz, "Clustered Voltage Scaling Technique for Low-Power Design", International Symposium on Low-Power Electronic Design, April 1995, pp. 3-8
8. S. Narendra, D. Antoniadis, and V. De, "Impact of Using Adaptive Body Bias to Compensate Die-to-die Vt Variation on Within-die Vt Variation", International Symposium on Low-Power Electronic Design, Aug. 1999, pp. 229-232