Ultra-low power DLMS adaptive filter for hearing aid applications

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 352-357

  Kim, H I ^a   Roy, K ^a  

^a Purdue University   (United States)

Author keywords

DLMS adaptive filter; Parallel architecture; Sub CMOS; Sub pseudo NMOS; Sub threshold operation

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ENERGY EFFICIENCY; HEARING AIDS; MOS DEVICES; OPTIMIZATION;

PARALLEL ARCHITECTURES;

ADAPTIVE FILTERING;

EID: 0034863491     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383182     Document Type: Conference Paper

References (10)

1. Feedback cancellation in hearing aids: Results from a computer simulation
2. Reducing acoustic feedback in hearing aids
3. Robust ultra-low power sub-threshold DTMOS logic
4. Ultra-low power digital sub-threshold logic circuits
5. Pipeline architecture of the LMS adaptive digital filter with the minimum output latency
6. A high sampling rate delayed LMS filter architecture