-
1
-
-
0035242870
-
Robust subthreshold logic for ultra-low power operation
-
Feb
-
Soeleman, K. Roy, and B. Paul, "Robust subthreshold logic for ultra-low power operation," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 1, pp. 90-99, Feb. 2001.
-
(2001)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.9
, Issue.1
, pp. 90-99
-
-
Soeleman, K.R.1
Paul, B.2
-
2
-
-
0034860181
-
Low-power CMOS at Vdd = 4kT/q
-
A. Bryant, J. Brown, P. Cottrell, M. Ketchen, J. Ellis-Monaghan, and E. J. Nowak, "Low-power CMOS at Vdd = 4kT/q," in Proc. Device Res. Conf., 2001, pp. 22-23.
-
(2001)
Proc. Device Res. Conf
, pp. 22-23
-
-
Bryant, A.1
Brown, J.2
Cottrell, P.3
Ketchen, M.4
Ellis-Monaghan, J.5
Nowak, E.J.6
-
3
-
-
28444444598
-
Analysis and mitigation of variability in subthreshold design
-
Aug
-
B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, "Analysis and mitigation of variability in subthreshold design," in Proc. Int. Symp. Low Power Electron. Design, Aug. 2005, pp. 20-25.
-
(2005)
Proc. Int. Symp. Low Power Electron. Design
, pp. 20-25
-
-
Zhai, B.1
Hanson, S.2
Blaauw, D.3
Sylvester, D.4
-
4
-
-
0017503796
-
CMOS analog integrated circuits based on weak inversion operations
-
Jun
-
E. Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak inversion operations," IEEE J. Solid-State Circuits, vol. 12, no. 3, pp. 224-231, Jun. 1977.
-
(1977)
IEEE J. Solid-State Circuits
, vol.12
, Issue.3
, pp. 224-231
-
-
Vittoz, E.1
Fellrath, J.2
-
5
-
-
11944273157
-
A 180-mV subthreshold FFT processor using a minimum energy design methodology
-
Jan
-
A. Wang and A. P. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.1
, pp. 310-319
-
-
Wang, A.1
Chandrakasan, A.P.2
-
7
-
-
28144440165
-
Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90 nm CMOS
-
Feb
-
B. Calhoun and A. Chandrakasan, "Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90 nm CMOS," in Proc. Int. Solid-State Circuits Conf., Feb. 2005, pp. 300-301.
-
(2005)
Proc. Int. Solid-State Circuits Conf
, pp. 300-301
-
-
Calhoun, B.1
Chandrakasan, A.2
-
8
-
-
0742286681
-
Ultra-low-power DLMS adaptive filter for hearing aid applications
-
Dec
-
C. H. Kim, H. Soeleman, and K. Roy, "Ultra-low-power DLMS adaptive filter for hearing aid applications," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 6, pp. 1058-1067, Dec. 2003.
-
(2003)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.11
, Issue.6
, pp. 1058-1067
-
-
Kim, C.H.1
Soeleman, H.2
Roy, K.3
-
9
-
-
4444275443
-
Double gate-MOSFET subthreshold circuit for ultra-low power applications
-
Sep
-
J. J. Kim and K. Roy, "Double gate-MOSFET subthreshold circuit for ultra-low power applications," IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1468-1474, Sep. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.9
, pp. 1468-1474
-
-
Kim, J.J.1
Roy, K.2
-
10
-
-
13344280331
-
Device optimization for digital subthreshold logic operation
-
Feb
-
B. C. Paul, "Device optimization for digital subthreshold logic operation," IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 237-247, Feb. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.2
, pp. 237-247
-
-
Paul, B.C.1
-
11
-
-
0018455052
-
VLSI limitations from drain-induced barrier lowering
-
Apr
-
R. R. Troutman, "VLSI limitations from drain-induced barrier lowering," IEEE Trans. Electron Devices, vol. ED-26, no. 4, pp. 461-469, Apr. 1979.
-
(1979)
IEEE Trans. Electron Devices
, vol.ED-26
, Issue.4
, pp. 461-469
-
-
Troutman, R.R.1
-
12
-
-
0024755327
-
Reverse short-channel effects on threshold voltage in submicrometer salicide devices
-
Oct
-
C. Y. Lu and J. M. Sung, "Reverse short-channel effects on threshold voltage in submicrometer salicide devices," IEEE Electron Device Lett., vol. 10, no. 10, pp. 446-148, Oct. 1989.
-
(1989)
IEEE Electron Device Lett
, vol.10
, Issue.10
, pp. 446-148
-
-
Lu, C.Y.1
Sung, J.M.2
-
13
-
-
0029545617
-
Reverse short channel effect and channel length dependence of boron penetration in PMOSFETs
-
Dec
-
C. Subramanian, "Reverse short channel effect and channel length dependence of boron penetration in PMOSFETs," in Int. Electron Device Meeting, Dec. 1995, pp. 423-426.
-
(1995)
Int. Electron Device Meeting
, pp. 423-426
-
-
Subramanian, C.1
-
14
-
-
34347222026
-
Subthreshold logical effort: A systematic framework for optimal subthreshold device sizing
-
Jul
-
J. Keane, T. Kim, H. Eom, and C. Kim, "Subthreshold logical effort: A systematic framework for optimal subthreshold device sizing," in Proc. Design Autom. Conf., Jul. 2006, pp. 425-428.
-
(2006)
Proc. Design Autom. Conf
, pp. 425-428
-
-
Keane, J.1
Kim, T.2
Eom, H.3
Kim, C.4
-
15
-
-
0032256253
-
25 nm CMOS design considerations
-
Y. Taur, C. H. Wann, and D. J. Frank, "25 nm CMOS design considerations," in Int. Electron Devices Meeting, 1998, pp. 789-792.
-
(1998)
Int. Electron Devices Meeting
, pp. 789-792
-
-
Taur, Y.1
Wann, C.H.2
Frank, D.J.3
-
16
-
-
34347266274
-
Suppression of the reverse short channel effect in sub-micron CMOS devices
-
Dec
-
M. Tohmason, J. Prasad, and J. De Greve, "Suppression of the reverse short channel effect in sub-micron CMOS devices," in Proc. Int. Semiconductor Device Res. Symp., Dec. 2003, pp. 420-421.
-
(2003)
Proc. Int. Semiconductor Device Res. Symp
, pp. 420-421
-
-
Tohmason, M.1
Prasad, J.2
De Greve, J.3
|