RT-level interconnect optimization in DSM regime

Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000

Volumn , Issue , 2000, Pages 143-148

  Katkoori, S ^a   Alupoaei, S ^a  

^a University of South Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ITERATIVE METHODS; MACROS; SIMULATED ANNEALING; SYSTEMS ANALYSIS;

CLUSTER GROWTH; CRITICAL NET; DATA PATH DESIGN; INTERCONNECT OPTIMIZATION; ITERATIVE IMPROVEMENTS; PRIMARY INPUTS; STATIC TIMING ANALYSIS; WIRE LENGTH;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 0009613218     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWV.2000.844543     Document Type: Conference Paper

References (10)

1. -. "The National Technology Roadmap for Semiconductors". SIA (Semiconductor Industry Association), 1997.
2. J. Cong, K. Y. Khoo, C. K. Koh, and Z. Pan. "Interconnect Design for Deep Submicron ICs". In Proceedings of International Conference on Computer Aided Design, pages 478-485, November 1997.
3. D.Sylvester and K.Kuetzer. "Getting to the bottom of deep submicron". In Proceedings of International Conference on Computer-Aided Design, pages 203-211. 1998.
4. A.B. Kahng et. al. Interconnect tuning strategies for high-performance ics. 1997.
5. J. Cong et. al. Performance optimization of vlsi interconnect layout. In Integration, the VLSI Journal, pages 1-94. 1996.
6. C. Tseng and D. P. Siewiorek. "Facet : A Procedure for the Automated Synthesis of Digital Systems". In 20th ACM/IEEE Design Automation Conference, pages 490-496, 1983.
7. A. Durbha and S. Katkoori. "RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime". pages -, 1999. X IFIP International Conference on Very Large Scale Integration.
8. R. W. Broderson, editor. Anatomy of a Silicon Compiler. Kluwer Academic Publishers, 1992.
9. C. Ratzlaff and L. T. Pillage. "RICE: Rapid Interconnect Circuit Evaluation Using Asymptotic Waveform Evaluation". IEEE Transactions on Computer-Aided Design of Circuits and Systems, pages 763-776, June 1994.
10. Electronic Products. "Novel IC Shuffles Parallel Processing Data". pages 42-50, August 1986.