Evaluation on power reduction applying gated clock approaches

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages

  Palumbo, G ^a   Pappalardo, F ^a   Sannella, S ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; CONSUMER ELECTRONICS; ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS;

GATED CLOCK; POWER REDUCTION; PROGRAMMABLE INTERRUPT CONTROLLER;

TIMING CIRCUITS;

EID: 0036292923     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. A survey of design techniques for system-level dynamic power management
2. Designing low-power circuits: Practical recipes
3. Automatic synthesis of gated clocks for power reduction in sequential circuits
4. Automatic synthesis of low-power gated-clocks finite-state machines
5. Individual flip-flops with gated clocks for low power datapaths
6. Clock gating and its application to low power design of sequential circuits
7. Power compiler: A gate level power optimization and synthesis system