Process-tolerant ultralow voltage digital subthreshold design

2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systms - Digest of Papers, SiRF

Volumn , Issue , 2008, Pages 42-45

  Roy, Kaushik ^a   Kulkarni, Jaydeep P ^a   Hwang, Myeong Eun ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; ELECTRONICS INDUSTRY; INTEGRATED CIRCUITS; MODULATION; NETWORKS (CIRCUITS); NONMETALS; PROCESS ENGINEERING; RADIOFREQUENCY SPECTROSCOPY; SILICON; STATIC RANDOM ACCESS STORAGE; VOLTAGE STABILIZING CIRCUITS; WAVE FILTERS;

BIT CELL; CIRCUIT TECHNIQUES; CMOS TECHNOLOGIES; IN-PROCESS; LEVEL CONVERTERS; MEMORY APPLICATIONS; PROCESS VARIATIONS; RF SYSTEMS; SCHMITT TRIGGERS; SUB THRESHOLD REGION; SUB-THRESHOLD DESIGN; ULTRA-LOW-VOLTAGE; VOLTAGE SCALING;

MONOLITHIC INTEGRATED CIRCUITS;

EID: 52049084842     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SMIC.2008.17     Document Type: Conference Paper

References (5)

1. H. Soeleman et al, Proc. of ISLPED, pp. 94-96, 1998
2. M.E. Hwang et al, Proc of VLSI Circuit Symp. 2007
3. J. P. Kulkarni et al, IEE Journal of Solid State Circuits, pp.2304-2310, Vol 42, No. 10. October 2007
4. B. H. Calhoun et al, ISSCC, pp. 628-629, Feb. 2006
5. Predictive Technology Models: online at http://www.eas.asu.edu/~ptm/