Effects of global interconnect optimizations on performance estimation of deep submicron design

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 56-61

  Cao, Yu ^a   Hu, Chenming ^a   Huang, Xuejue ^a   Kahng, Andrew B ^b   Muddu, Sudhakar ^c   Stroobandt, Dirk ^d   Sylvestel, Dennis ^e  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of California   (United States)

^c HEWLETT PACKARD ENTERPRISE   (United States)

^d GHENT UNIVERSITY   (Belgium)

^e SYNOPSYS INC   (United States)

Author keywords

Crosstalk noise; Inductance; Interconnect delay; System performance models; Technology extrapolation; VLSI

Indexed keywords

DESIGN; EXTRAPOLATION; INDUCTANCE; INTEGRATED CIRCUIT INTERCONNECTS; MICROSTRIP LINES; BUFFER CIRCUITS; CROSSTALK; DELAY CIRCUITS; ESTIMATION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; OPTIMIZATION; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

CAPACITIVE COUPLING NOISE; CROSSTALK NOISE; DEEP SUB-MICRON DESIGNS; INTERCONNECT DELAY; PERFORMANCE ESTIMATION; PERFORMANCE SIMULATION; SYSTEM PERFORMANCE MODEL; VLSI;

COMPUTER AIDED DESIGN;

CROSSTALK NOISE; DEEP SUBMICRON DESIGN; GLOBAL INTERCONNECT OPTIMIZATION; INTERCONNECT DELAY; TECHNOLOGY EXTRAPOLATION; WIRE SIZING MODEL;

EID: 0034477838     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896451     Document Type: Conference Paper

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