Robust subthreshold logic for ultra-low power operation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 1, 2001, Pages 90-99

  Soeleman, Hendrawan ^a,b   Roy, Kaushik ^a,b   Paul, Bipul C ^a,b  

^a IEEE   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

Subthreshold dynamic threshold voltage MOS (Sub DTMOS); Subthreshold logic; Variable threshold voltage subthreshold CMOS (VT Sub CMOS)

Indexed keywords

SUBTHRESHOLD DYNAMIC THRESHOLD VOLTAGE CMOS; SUBTHRESHOLD LOGIC; VARIABLE THRESHOLD VOLTAGE SUBTHRESHOLD CMOS;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOS DEVICES; MULTIPLYING CIRCUITS; THERMAL EFFECTS; THERMODYNAMIC STABILITY; THRESHOLD VOLTAGE;

LOGIC CIRCUITS;

EID: 0035242870     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.920822     Document Type: Article

References (10)

1. A multi-level approach to low-power IC design
2. Low-power CMOS digital design
3. Low-power digital design
4. Ultra-low power digital subthreshold logic circuits
5. Digital CMOS logic operation in the sub-threshold region
6. 2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme
7. Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation
8. Positive/negative high voltage charge pump system
9. Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI
10. Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS