On the optimization power of redundancy addition and removal for sequential logic optimization

Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001

Volumn , Issue , 2001, Pages 292-299

  Millan E S ^a   Entrena, L ^a   Espejo, J A ^a  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC SYNTHESIS; RECONFIGURABLE HARDWARE; REDUNDANCY; SYSTEMS ANALYSIS;

LOGIC OPTIMIZATION; RESYNTHESIS; RETIMING; SEQUENTIAL LOGIC OPTIMIZATION;

COMPUTER CIRCUITS;

EID: 84969506377     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2001.952305     Document Type: Conference Paper

References (10)

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