Large random telegraph noise in sub-threshold operation of nano-scale nMOSFETs

2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Volumn , Issue , 2009, Pages 17-20

  Campbell, J P ^a   Yu, L C ^a,b   Cheung, K P ^a   Qin, J ^a,c   Suehle, J S ^a   Oates, A ^d   Sheng, K ^b  

^a NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY   (United States)

^b RUTGERS UNIVERSITY   (United States)

^c UNIVERSITY OF MARYLAND   (United States)

^d TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

RTN; Sub VTH operation

Indexed keywords

CHANNEL DIMENSION; LOW POWER APPLICATION; LOW-FREQUENCY NOISE; LOW-FREQUENCY NOISE MEASUREMENTS; NANO SCALE; NMOSFETS; RANDOM TELEGRAPH NOISE; SCALED DEVICES; SUBTHRESHOLD; SUBTHRESHOLD OPERATION; VIABLE SOLUTIONS;

HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUITS; TELEGRAPH; THERMAL NOISE;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 75649142725     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2009.5166255     Document Type: Conference Paper

References (17)

1. S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak, and D. M. Sylvester, "Ultralow-voltage, minimum-energy CMOS" Ibm J Res Dev, 50, pp. 469-490 (2006)
2. S. Hanson, M. Seok, D. Sylvester, and D. Blaauw, "Nanometer device scaling in subthreshold logic and SRAM" IEEE Trans. Electron Dev, 55, pp. 175-185 (2008)
3. I. J. Chang, J. J. Kim, S. P. Park, and K. Roy, "A 32 KB 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS" IEEE J. Solid-St Circ, 44, pp. 650-658 (2009)
4. t Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter" Proc. of the IEEE International Solid-State Circuits Conference pp. 318-319, 616 (2008)
5. B. H. Calhoun and A. P. Chandrakasan, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS" IEEE J. Solid-St Circ, 41, pp. 1673-1679 (2006)
6. K. S. Ralls, W. J. Skocpol, L. D. Jackel, R. E. Howard, L. A. Fetter, R. W. Epworth, and D. M. Tennant, "Discrete Resistance Switching in Submicrometer Silicon Inversion-Layers - Individual Interface Traps and Low-Frequency (1-F Questionable) Noise" Phys Rev Lett, 52, pp. 228-231 (1984)
7. P. Fantini, A. Ghetti, A. Marinoni, G. Ghidini, A. Visconti, and A. Marmiroli, "Giant Random Telegraph Signals in Nanoscale Floating-Gate Devices" IEEE Electron Device Lett., 28, pp. 1114-1116 (2007)
8. H. Kurata, K. Otsuga, A. Kotabe, S. Kajiyama, T. Osabe, Y. Sasago, S. Narumi, K. Tokami, S. Kamohara, and O. Tsuchiya, "Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node" IEEE J. Solid-St Circ, 42, pp. 1362-1369 (2007)
9. N. Tega, H. Miki, M. Yamaoka, H. Kume, M. Toshiyuki, T. Ishida, M. Yuki, R. Yamada, and T. Kazuyoshi, "Impact of Threshold Voltage Fluctuation Due to Random Telegraph Noise on Scaled-Down SRAM" IEEE Int. Rel. Phys. Symp. pp. 541-546 (2008)
10. E. Simoen and C. Claeys, "Gate Length Effect on the RTS Noise Amplitude in SOI MOSFET's" IEEE Electron Device Lett., 17, pp. 181-183 (1996)
11. S. T. Martin, G. P. Li, E. Worley, and J. White, "The Gate Bias and Geometry Dependence of Random Telegraph Signal Amplitudes" IEEE Electron Device Lett., 18, pp. 444-446 (1997)
12. M. H. Tsai and T. P. Ma, "The Impact of Device Scaling on the Current Fluctuations in Mosfets" IEEE Trans. Electron Dev, 41, pp. 2061-2068 (1994)
13. A. Asenov, R. Balasubramaniam, A. R. Brown, J. H. Davies, and S. Saini, "Random Telegraph Signal Amplitudes in Sub-100 nm (Decanano) MOSFETs: a 3D 'Atomistic' Simulation Study" IEEE Int. Electron. Dev. Meeting pp. 279-282 (2000)
14. A. Asenov, R. Balasubramaniam, A. R. Brown, and J. H. Davies, "RTS Amplitudes in Decananometer MOSFETs: 3-D Simulation Study" IEEE Trans. Electron Dev, 50, pp. 839-845 (2003)
15. M. J. Kirton and M. J. Uren, "Noise in Solid-State Microstructures - A New Perspective on Individual Defects, Interface States and Low-Frequency (1/F) Noise" Adv Phys, 38, pp. 367-468 (1989)
16. K. K. Hung, P. K. Ko, C. M. Hu, and Y. C. Cheng, "A Unified Model for the Flicker Noise in Metal Oxide-Semiconductor Field-Effect Transistors" IEEE Trans. Electron Dev, 37, pp. 654-665 (1990)
17. 2 Interface" J Appl Phys, 68, pp. 200-204 (1990)