Evaluating PICA capability for future low voltage SOI chips

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2008, Pages 407-416

  Stellari, Franco ^a   Song, Peilin ^a   Vickers, Jim ^b   Shaw, Chris ^b   Kasapi, Steven ^c   Ispasoiu, Radu ^d  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b DCG SYSTEMS INC   (United States)

^c NVIDIA   (United States)

^d Fairchild Imaging   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

65NM TECHNOLOGIES; BULK SILICON TECHNOLOGIES; INGAAS DETECTORS; LOW VOLTAGES; SIGNAL-TO-NOISE RATIOS; SOI TECHNOLOGIES; SPECIFIC TOOLS; SUPPLY VOLTAGES; TEST CHIPS; TIME-RESOLVED EMISSIONS;

ACOUSTIC INTENSITY; QUALITY ASSURANCE; SAFETY FACTOR; SIGNAL TO NOISE RATIO; SILICON DETECTORS; TECHNOLOGY;

FAILURE ANALYSIS;

EID: 63549104342     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1361/cp2008istfa407     Document Type: Conference Paper

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