Time-resolved measurements of self-heating in SOI and strained-silicon MOSFETs using photon emission microscopy

IEEE Electron Device Letters

Volumn 25, Issue 4, 2004, Pages 208-210

  Polonsky, Stas ^a   Jenkins, Keith A ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Channel temperature; Field effect transistor (FET); Metal oxide semiconductor field effect transistor (MOSFET); Picosecond imaging circuit analysis (PICA); Self heating; Silicon on insulator (SOI); Strained silicon

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; EMISSION SPECTROSCOPY; HEATING; LEAKAGE CURRENTS; LUMINESCENCE; OPTICAL VARIABLES MEASUREMENT; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY;

CHANNEL TEMPERATURE; DRAIN VOLTAGE; PHOTON EMISSION MICROSCOPY; PICOSECOND IMAGING CIRCUIT ANALYSIS; SELF HEATING;

MOSFET DEVICES;

EID: 1942455774     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.825192     Document Type: Letter

References (19)

1. L. J. McDaid, S. Hall, P. Mellor, W. Eccleston, and J. Alderman, "Physical origin of the negative differential resistance in SOI transistors," Electron. Lett., vol. 25, pp. 827-828, 1989.
2. D. A. Dallmann and K. Shenai, "Scaling constraints imposed by self-heating in submicron SOI MOSFET's," IEEE Trans. Electron Devices, vol. 42, pp. 489-496, Mar. 1995.
3. P. Su, K. Goto, T. Sugii, and C. Hu, "Excess hot-carrier currents in SOI MOSFETs and its implications," in Proc. IRPS, 2002, pp. 93-97.
4. J. Roig, D. Flores, M. Vellvehi, J. Rebollo, and J. Millan, "Novel techniques for reducing self-heating effects in silicon-on-insulator power devices," in Proc. Int. Semicond. Conf., vol. 2, Oct. 2001, pp. 493-496.
5. B. Tenbroek, M. Lee, W. Redman-White, R. Bunyan, and M. Uren, "Impact of self-heating and thermal coupling on analog circuits in SOI CMOS," IEEE J. Solid-State Circuits, vol. 33, pp. 1037-1046, July 1998.
6. L. McDaid, S. Hall, W. Eccleston, and J. Alderman, "Monitoring the temperature rise in SOI transistors by measurement of leakage current," in Proc. SOI Conf., 1991, pp. 28-29.
7. R. Bunyan, M. Uren, J. Alderman, and W. Eccleston, "Use of noise thermometry to study the effects of self-heating in submicrometer SOI MOSFETs," IEEE Electron Device Lett., vol. 13, pp. 279-281, May 1992.
8. L. T. Su, K. E. Goodson, D. A. Antoniadis, M. I. Flik, and J. E. Chung, "Measurement and modeling of self-heating effects in SOI nMOSFETs," in IEDM Tech. Dig., Dec. 1992, pp. 349-352.
9. K. Jenkins and J. Y.-C. Sun, "Measurement of I-V curves of silicon-on-insulator SOI MOSFETs without self-heating," IEEE Electron Device Lett., vol. 16, pp. 139-141, Apr. 1995.
10. K. A. Jenkins and K. Rim, "Measurement of the effect of self-heating in strained-silicon MOSFETs," IEEE Electron Device Lett., vol. 23, pp. 360-362, June 2002.
11. W. Jin, S. Fung, W. Liu, P. C. H. Chan, and C. Hu, "Self-heating characterization for SOI MOSFET based on ac output conductance," in IEDM Tech. Dig., Dec. 1999, pp. 175-178.
12. J. C. Tsang and J. A. Kash, "Picosecond hot electron light emission from submicron complimentary metal-oxid-semiconductor circuit," Appl. Phys. Lett., vol. 70, pp. 889-891, 1997.
13. J. A. Kash and J. C. Tsang, "Dynamic internal testing of CMOS circuits using hot luminescence," IEEE Electron Device Lett., vol. 18, no. 7, pp. 330-332, 1997.
14. S. Polonsky et al., "Noninvasive timing analysis of IBM G6 microprocessor L1 cache using backside time-resolved hot electron luminescence," in Proc. ISSCC, 2000, pp. 222-223.
15. S. Polonsky, A. Weger, and M. McManus, "Picosecond imaging circuit analysis of leakage currents in CMOS circuits," in Proc. ISTFA, Nov. 2002, pp. 387-390.
16. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.
17. N. Goldblatt, M. Leibowitz, and W. Lo, "Unique and practical IC timing analysis tool utilizing intrinsic photon emission," Microelectron. Reliabil., vol. 41, no. 9-10, pp. 1507-1512, 2001.
18. D. Bodoh, E. Black, K. Dickson, R. Wang, T. Cheng, N. Pakdaman, J. Vickers, D. Cotton, and B. Lee, "Defect localization using time-resolved photon emission on SOI devices that fail scan tests," in Proc. ISTFA, Nov. 2002, pp. 655-661.
19. P. Smeys et al., "A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric," in VLSI Symp. Tech. Dig., 2000, pp. 184-185.