A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 um2 SRAM cell

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 61-64

  Thompson, S ^a   Anand, N ^a   Armstrong, M ^a   Auth, C ^a   Arcot, B ^a   Alavi, M ^a   Bai, P ^a   Bielefeld, J ^a   Bigwood, R ^a   Brandenburg, J ^a   Buehler, M ^a   Cea, S ^a   Chikarmane, V ^a   Choi, C ^a   Frankovic, R ^a   Ghani, T ^a   Glass, G ^a   Han, W ^a   Hoffmann, T ^a   Hussein, M ^a   Jacob, P ^a   Jain, A ^a   Jan, C ^a   Joshi, S ^a   Kenyon, C ^a   Klaus, J ^a   Klopcic, S ^a   Luce, J ^a   Ma, Z ^a   McIntyre, B ^a   Mistry, K ^a   Murthy, A ^a   Nguyen, P ^a   Pearson, H ^a   Sandford, T ^a   Schweinfurth, R ^a   Shaheed, R ^a   Sivakumar, S ^a   Taylor, M ^a   Tufts, B ^a   Wallace, C ^a   Wang, P ^a   Weber, C ^a   Bohr, M ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN; LOGIC GATES; MOS DEVICES; SEMICONDUCTING SILICON; STATIC RANDOM ACCESS STORAGE;

STRAINED SILICON CHANNEL;

TRANSISTORS;

EID: 0036931972     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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