Analysis of 0.13 um CMOS technology using time resolved light emission

Proceedings of the 30th International Symposium for Testing and Failure Analysis, ISTFA 2004

Volumn , Issue , 2004, Pages 203-209

  Ouimet, Peter ^a   Goertz, Jason ^a   Rinaudo, Olivier ^a   Long, Lousinda ^a   Yeung, Simon ^a  

^a FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; LIGHT EMISSION; MICROPROCESSOR CHIPS; PROBABILITY; SILICON; WAVEFORM ANALYSIS;

AUTOMATIC TEST PROGRAM GENERATION (ATPG); DIAGNOSTIC FAULT SIMULATION (DFS); SYSTEM ON A CHIP (SOC); TIME RESOLVED LIGHT EMISSION (TRLEM);

CMOS INTEGRATED CIRCUITS;

EID: 10444288970     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. th International Symposium for Testing and Failure Analysis (ISTFA), p 655 (2002).
2. th International Symposium for Testing and Failure Analysis (ISTFA), p 179 (2001).
3. J. B. Colvin, "BGA and Advanced Package Wire to Wire Bonding for Backside Emission Microscopy," Proceedings 25th International Symposium for Testing and Failure Analysis (ISTFA), p 365 (1999).