Latchup Analysis Using Emission Microscopy

Microelectronics Reliability

Volumn 43, Issue 9-11, 2003, Pages 1603-1608

  Stellari, Franco ^a   Song, Peilin ^a   McManus, Moyra K ^a   Weger, Alan J ^a   Gauthier, Robert ^b   Chatty, Kiran V ^b   Muhammad, Mujahid ^b   Sanda, Pia ^c   Wu, Philip ^c   Wilson, Steve ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM MICROELECTRONICS   (United States)

^c IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; CMOS INTEGRATED CIRCUITS; ELECTROSTATICS; MICROSCOPIC EXAMINATION;

ELECTRICAL STIMULATION;

FLIP FLOP CIRCUITS;

EID: 0043195514     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(03)00281-6     Document Type: Conference Paper

References (12)

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2. R.R. Troutman, Latchup in CMOS technology, Bottom: Kluwer Academy, 1986.
3. Y. Taur, WH. Chang and R.H. Dennard, "Characterization and modeling of a latch-up free 1-μm CMOS technology", IEDM Tech. Dig., 1984, pp. 389-401.
4. R.S. Payne, W.R. Grant and W.J. Bertram, "Elimination of latch-up in bulk CMOS", IEDM Tech. Dig., 1980, pp. 248-251.
5. E. Sangiorgi, M.R. Pinto, S.E, Swirhum and R.W. Dutton, 'Two dimensional numerical analysis of latchup in VLSI CMOS technlogy", IEEE Trans. Electron Dev., vol 32, 1985, pp. 2117-2130.
6. "JESD78 latchup testing standard", Electronic Industry Association JEDEC standards, Arlington, VA.
7. M. Kyomasu, T. Araki, T. Ohtsuki and M. Nakamura, "Anlysis of latchup in bulk CMOS IC", Trans. IECE Japan, vol. C61, 1978, pp. 106-113.
8. P.V. Dressendorfer and M.G. Armeadariz, "A SEM technique for experimentally locating latchup paths in integrated circuits", IEEE Trans. Nuclear Science, vol. 27, 1980, pp. 1735-1738.
9. J.Quincke, C. Boit, D. Fuehrer, "Electroluminescence Measurements with Temporal and Spatial Resolution for Latch-up Investigations", Microel. Eng., vol. 12, 1990, pp. 157-162.
10. A.J. Weger, S. Voldman, F. Stellari, P. Song, P. Sanda, M.K, McManus, "Transimssion line pulse picosecond imaging circuit analysis methodology for evaluation of ESD and latchup", International Reliability Physics Symposium, 2003, pp. 99-104.
11. T. Aoki and A. Yoshii, "Analysis of latchup-induced photo emissions'', IEEE Trans. Electron Dev., vol. 37, no. 9, 1990, pp. 2080-2083.
12. "C4880-21 user manual", Hamamatsu Photonica K.K.