Study of Critical Factors Determining Latchup Sensitivity of ICs using Emission Microscopy

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn 2003-November, Issue , 2003, Pages 19-24

  Stellari, Franco ^a   Song, Peilin ^a   McManus, Moyra K ^a   Weger, Alan J ^a   Gauthier, Robert J ^b   Chatty, Kiran V ^b   Muhammad, Mujahid ^b   Sanda, Pia ^c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM MICROELECTRONICS   (United States)

^c IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROSTATIC DEVICES; FLIP FLOP CIRCUITS; INTEGRATED CIRCUITS;

COMMERCIAL CHIPS; CRITICAL FACTORS; EMISSION MICROSCOPY; INPUT-OUTPUT; LATCH-UPS; OUTPUT CIRCUITS; TEST CHIPS; VLSI CHIP;

TIMING CIRCUITS;

EID: 3042659380     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.31399/asm.cp.istfa2003p0019     Document Type: Conference Paper

References (8)

1. T. Kessler and F.W. Wulfert, "Diagnosing latch-up with backside emission microscopy", Semiconductor International, no. 7, 2000.
2. T. Aoki and A. Yoshii, "Analysis of latchup-induced photon emissions", IEEE Trans. Electron Dev., vol. 37, no. 9, 1990, pp. 2080-2083.
3. P. Salome, C. Leroux, J.P. Chante, P. Crevel and G. Reimbold, "Study of a 3D phenomenon during ESD stress in deep submicron CMOS technologies using photon emission tool", International Reliability Physics Symposium, 1997, pp. 325-332.
4. R.R. Troutman, "Latchup in CMOS technology", Kluwer Academy Publisher, Boston, MA, 1986.
5. H.B. Bakoglu, "Circuits, interconnections, and packaging for VLSI", Addison Wesley publications, 1990.
6. M.J. Hargrove, S. Voldman, R. Gauthier, J. Brown, K. Duncan and W. Craig, "Latchup in CMOS technology", International Reliability Physics Symposium, 1998, pp. 269-278.
7. "JESD78 latchup testing standard", Electronic Industry Association JEDEC standards, Arlington, VA (www.jedec.org).
8. "C4880-21 user manual", Hamamatsu Photonics K.K.