Extremely scaled silicon nano-CMOS devices

Proceedings of the IEEE

Volumn 91, Issue 11, 2003, Pages 1860-1872

  Chang, Leland ^a   Choi, Yang Kyu ^a   Ha, Daewon ^a   Ranade, Pushkar ^a   Xiong, Shiying ^a   Bokor, Jeffrey ^a   Hu, Chenming ^b,c   King, Tsu Jae ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

CMOS; FinFET; Metal gate; Molybdenum; MOSFET; Nanotechnology; Scaling, ultrathin body (UTB)

Indexed keywords

CARRIER MOBILITY; CRYSTAL ORIENTATION; MOLYBDENUM; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; NETWORKS (CIRCUITS); SILICON; SILICON ON INSULATOR TECHNOLOGY; SURFACE ROUGHNESS;

CMOS; FINFET; METAL GATES; MOSFET; SCALING; ULTRATHIN BODY (UTB);

CMOS INTEGRATED CIRCUITS;

EID: 5744251698     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2003.818336     Document Type: Conference Paper

References (67)

1. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFET's and their application dependencies," Proc. IEEE, vol. 89, pp. 259-288, Mar. 2001.
2. International Technology Roadmap for Semiconductors, 2001.
3. J. Welser, J. Hoyt, S. Takagi, and J. F. Gibbons, "Strain dependence of the performance enhancement in strained-Si n-MOSFETs," in Int. Electron Devices Meeting Tech. Dig., 1994, pp. 373-376.
4. C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, "A comparative study of advanced MOSFET concepts," IEEE Trans. Electron Devices, vol. 43, pp, 1742-1753, Oct. 1996.
5. H.-S. P. Wong, "Beyond the conventional transistor," in IBM J. Res. Develop., 2002, vol. 46, pp. 133-168.
6. B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M.-R. Lin, "15 nm gate length planar CMOS transistor," in Int. Electron Devices Meeting Tech. Dig., 2001, pp. 937-939.
7. S. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V. Subramanian, J. Bokor, T.-J. King, and C. Hu, "FinFET: a quasi-planar double-gate MOSFET," in 2001 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2000, pp. 118-119.
8. T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettier, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," in Symp. VLSI Technology Dig. Tech. Papers, 2000, pp. 174-175.
9. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's: part I - effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, pp. 2357-2362, Dec. 1994.
10. Y. Taur, C. H. Wann, and D. J. Frank, "25 nm CMOS design considerations," in Int. Electron Devices Meeting Tech. Dig., 1998, pp. 789-792.
11. L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, "Gate-length scaling and threshold voltage control of double-gate MOSFETs," in Int. Electron Devices Meeting Tech. Dig., 2000, pp. 719-722.
12. J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C. P. Willets, A. Johnson, S. P. Cole, H. E. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. E. Cottrell, M. Ieong, and H.-S. P. Wong, "High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices," in Int. Electron Devices Meeting Tech. Dig., 2001, pp. 437-440.
13. MEDICI v2000.2 User's Manual, Avant! Corp., 2000.
14. K. Banoo and M. S. Lundstrom, "Electron transport in a model Si transistor," Solid State Electron., vol. 44, no. 9, pp. 1689-1695, Sept. 2000.
15. Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, "Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs," IEEE Electron Device Lett., vol 14, pp. 569-571, Dec. 1993.
16. S. E. Laux, A. Kumar, and M. V. Fischetti, "QDAME simulation of 7.5 nm double-gate Si nFET's with differing access geometries," in Int. Electron Devices Meeting Tech. Dig., 2002, pp. 715-718.
17. D. J. Frank, S. E. Laux, and M. V. Fischetti, "Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?," in Int. Electron Devices Meeting Tech. Dig., 1992, pp. 553-556.
18. D. A. Antoniadis, "MOSFET scalabillty limits and new frontier devices," in 2002 Symp. VLSI Technology Dig. Tech. Papers, 2002, pp. 2-5.
19. R. Lin, Q. Lu, P. Ranade, T.-J. King, and C. Hu, "An adjustable work function technology using Mo gate for CMOS devices," IEEE Electron Device Lett., vol. 23, pp. 49-51, Jan. 2002.
20. 2 gate dielectric," in 2002 Symp. VLSI Technology Dig. Tech. Papers, June 2002, pp. 24-25.
21. V. Misra, H. Zhong, and H. Lazar, "Electrical properties of Ru-based alloy gate electrodes for dual metal gate Si-CMOS," IEEE Electron Device Lett., vol. 23, pp. 354-356, June 2002.
22. B.-Y. Tsui and C.-F. Huang, "Wide range work function modulation of binary alloys for MOSFET application," IEEE Electron Device Lett., vol. 24, pp. 153-155, Mar. 2003.
23. A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. Ozawa, G. Minamihaba, H. Yano, K. Hieda, K. Suguro, T. Arikado, and K. Okumura, "High performance metal gate MOSFET's fabricated by CMP for 0.1 μm regime," in Int. Electron Devices Meeting Tech. Dig., 1998, p. 785.
24. I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, "Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion," IEEE Electron Device Lett., vol. 23, pp. 200-202, Apr. 2002.
25. Y.-C. Yeo, Q. Lu, P. Ranade, H. Takeuchi, K. J. Yang, I. Polishchuk, T.-J. King, C. Hu, S. C. Song, H. F. Luan, and D.-L. Kwong, "Dual-metal gate CMOS technology with ultra-thin silicon nitride gate dielectric," IEEE Electron Device Lett., vol. 22, pp. 227-229, May 2001.
26. P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen, and T.-J. King, "Tunable work function molybdenum gate technology for FDSOI-CMOS," in Int. Electron Devices Meeting Tech. Dig., Dec. 2002, pp. 363-366.
27. D. Ha, P. Ranade, Y.-K. Choi, J.-S. Lee, T.-J. King, and C. Hu, "Ultra-thin body silicon-on-insulator (UTB-SOI) MOSFET with metal gate work-function engineering for sub-70 nm technology node," in Extended Abstracts 2002 Int. Conf. Solid Slate Devices and Materials, 2002, pp. 782-783.
28. H. Wakabayashi, Y. Saito, K. Takeuchi, T. Mogami, and T. Kunio, "A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film," IEEE Trans. Electron Devices, vol. 48, pp. 2363-2369, Oct. 2001.
29. H. B. Michaelson, "The workfunction of the elements and its periodicity," J. Appl. Physics, vol. 48, no. 11, pp. 4729-4733, Nov. 1977.
30. R. Smoluchowski, "Anisotropy of the electronic work function of metals," Phys. Rev., vol. 60, pp. 661-674, 1941.
31. + ion implantation for the work function control," in Materials Research Society Symp. Proc., vol. 716, 2002, pp. B7.5.1-B7.5.6.
32. R. J. P. Lander, J. C. Hooker, J. P. van Zijl, F. Roozeboom, M. P. M. Maas, Y. Tamminga, and R. A. M. Wolters, "A tunable metal gate work function using solid state diffusion of nitrogen," in Proc. ESSDERC, 2002, pp. 103-106.
33. Y.-C. Yeo, P. Ranade, T.-J. King, and C. Hu, "Effects of high-κ gate dielectric materials on metal and silicon gate workfunctions," IEEE Electron Device Lett., vol. 23, pp. 342-344, June 2002.
34. Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Ultra-thin body SOI MOSFET for deep-sub-tenth micron era," in Int. Electron Devices Meeting 1998 Tech. Dig., 1999, pp. 919-921.
35. S.-D. Kim, C.-M. Park, and J. C. S. Woo, "Advanced model and analysis of series resistance for CMOS scaling into nanometer regime - part II quantitative analysis," IEEE Trans. Electron Devices, vol. 49, pp. 467-472, Mar 2002.
36. B. Doyle, R. Arghavani, D. Barlage, S. Datta, M. Doczy, J. Kavalieros, A. Murthy, and R. Chau, "Transistor elements for 30 nm physical gate lengths and beyond," Intel Tech. J., vol. 6, pp. 42-54, May 2002.
37. B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R. A. Roy, O. Dokumaci, Z. Ren, F.-F. Jamin, L. Shi, W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E. C. Jones, R. J. Miller, H.-S. P. Wong, and W. Haensch, "Extreme scaling with ultra-thin Si channel MOSFETs," in Int. Electron Devices Meeting Tech. Dig., 2002, pp. 267-270.
38. S. Zimin, L. Litian, and L. Zhijian, "Optimization of MOSFET's with polysilicon-elevated source/drain," in Proc. 5th Int. Conf. Solid-State and Integrated Circuit Technology, 1998, pp. 188-189.
39. W. B. De Boer, D. Terpstra, and J. G. M. Van Berkum, "Selective versus nonselective growth of Si and SiGe," Mater. Sci. Eng., vol. B67, pp. 46-52, 1999.
40. Y.-K. Choi, D. Ha, T.-J. King, and C. Hu, "Nanoscale ultrathin body PMOSFET's with raised selective germanium source/drain," IEEE Electron Device Lett., vol. 22, pp. 447-448, Sept. 2001.
41. S. P. Ashburn, M. C. Ozturk, G. Harris, and D. M. Maher, "Phase transitions during solid-state formation of cobalt germanide by rapid thermal annealing," J. Appl. Phys., vol. 74, no. 7, pp. 4455-4460, 1993.
42. S. P. Ashburn, M. C. Ozturk, J. J. Wortman, G. Harris, J. Honeycutt, and D. M. Maher, "Formation of titanium and cobalt germanides on Sl(100) using rapid thermal processing," J. Electron. Mater., vol. 21, no. 1, pp. 81-86, 1992.
43. R. Chau, J. Kavalieros, B. Doyle, A. Murthy, N. Paulsen, D. Lionberger, D. Barlage, R. Arghavani, B. Roberds, and M. Doczy, "A 50 nm depleted-substrate CMOS transistor (DST)," in Int. Electron Devices Meeting 1998 Tech. Dig., 2001, pp. 621-624.
44. H. van Meer and K. De Meyer, "The spacer/replacer concept: a viable route for sub-100 nm ultrathin-fllm fully-depleted SOI CMOS," IEEE Electron Device Lett., vol. 23, pp. 46-48, Jan. 2002.
45. H.-S. P. Wong, D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J. Welser, "Nanoscale CMOS," Proc. IEEE, vol. 87, pp. 537-570, Apr. 1999.
46. S.-H. Oh, J. M. Hergenrother, T. Nigam, D. Monroe, F. P. Klemens, A. Kornblit, W. M. Mansfield, M. R. Baker, D. L. Barr, F. H. Baumann, K. J. Bolan, T. Boone, N. A. Ciampa, R. A. Cirelli, D. J. Eaglesham, E. J. Ferry, A. T. Fiory, J. Frackoviak, J. P. Garno, H. J. Gossmann, J. L. Grazul, M. L. Green, S. J. Hillenius, R. W. Johnson, R. C. Keller, C. A. King, R. N. Kleiman, J. T.-C. Lee, J. F. Miner, M. D. Morris, C. S. Rafferty, J. M. Rosamllia, K. Short, T. W. Sorsch, A. G. Timko, G. R. Weber, G. D. Wilk, and J. D. Plummer, "50 nm vertical replacement gate (VRG) pMOSFETs," in Int. Electron Devices Meeting Tech. Dig., 2000, pp. 65-68.
47. J.-H. Lee, G. Taraschi, A. Wei, T. A. Langdo, E. A. Fitzgerald, and D. A. Antoniadis, "Super self-aligned double-gate (SSDG) MOSFET's utilizing oxidation rate difference and selective epitaxy," in Int. Electron Devices Meeting Tech. Dig., 1999, pp. 71-74.
48. H.-S. P. Wong, K. K. Chan, and Y. Taur, "Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel," in Int. Electron Devices Meeting Tech. Dig., 1997, pp. 427-430.
49. T. Su, J. P. Denton, and G. W. Neudeck, "New planar self-aligned double-gate fully-depleted p-MOSFET's using epitaxial lateral overgrowth (ELO) and selectively grown source/drain (S/D)," in Proc. IEEE Int. SOI Conf., 2000, pp. 110-111.
50. D. Hisamoto, T. Kaga, and E. Takeda, "Impact of the vertical SOI 'DELTA structure on planar device technology," IEEE Trans. Electron Devices, vol. 38, pp. 1419-1424, June 1991.
51. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub-50 nm p-channel FinFET," IEEE Trans. Electron Devices, vol. 48, pp. 880-886, May 2001.
52. N. Lindert, L. Chang, Y.-K. Choi, E. H. Andereon, W.-C. Lee, T.-J. King, and C. Hu, "Sub-60-nm quasiplanar FinFET's fabricated using a simplified process," IEEE Electron Device Lett., vol. 22, pp. 487-489, Oct. 2001.
53. Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "Sub-20 nm CMOS FinFET technologies," in Int. Electron Devices Meeting Tech. Dig., 2001, pp. 421-424.
54. F.-L. Yang, H.-Y. Chen, F.-C. Chen, Y.-L. Chan, K.-N. Yang, C.-J. Chen, H.-J. Tao, Y.-K. Choi, M.-S. Liang, and C. Hu, "35 nm CMOS FinFETs,"in Symp. VLSI Technology Tech. Dig., 2002, pp. 104-105.
55. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, and C. Hu, "FinFET scaling to 10 nm gate length," in Int. Electron Devices Meeting, 2002, pp. 251-254.
56. M. Shoji and S. Horiguchi, "Electronic structures and phononlimited electron mobility double-gate silicon-on-insulator Si inversion layers," J. Appl. Phys., vol. 85, pp. 2722-2731, 1999.
57. H. Majima, H. Ishikuro, and T. Hiramoto, "Threshold voltage increase by quantum mechanical narrow channel effect in ultra-narrow MOSFETs," in Int. Electron Devices Meeting Tech. Dig., 2001, pp. 379-382.
58. K. Asano, Y.-K. Choi, T.-J. King, and C. Hu, "Patterning sub-30-nm MOSFET gate with I-line lithography," IEEE Trans. Electron Devices, vol. 48, pp. 1004-1006, May 2001.
59. J. T. Horstmann, U. Hilleringmann, and K. F. Goser, "Matching analysis of deposition defined 50-nm MOSFET's," IEEE Trans. Electron Devices, vol. 45, pp. 299-306, Jan. 1998.
60. Y.-K. Choi, T.-J. King, and C. Hu, "A spacer patterning technology for nanoscale CMOS," IEEE Trans. Electron Devices, vol. 49, pp. 436-441, Mar. 2002.
61. _, "Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era," Solid State Electron., vol. 46, pp. 1595-1601, 2002.
62. Y.-K. Choi, L. Chang, P. Ranade, J.-S. Lee, D. Ha, S. Balasubramanian, A. Agarwal, M. Ameen, T.-J. King, and J. Bokor, "FinFET process refinements for improved mobility and gate work function engineering," in Int. Electron Devices Meeting Tech. Dig., 2002, pp. 259-262.
63. T. Sato, Y. Takeishi, and H. Hara, "Mobility anisotropy of electrons in inversion layers on oxidized silicon surfaces," Phy. Rev. B, vol. 4, pp. 1950-1960, 1971.
64. R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Arghavani, and S. Datta, "Advanced depicted-substrate transistor: single-gate, double-gate and tri-gate," in Proc. Solid State Devices and Materials, 2002, pp. 68-69.
65. J. Colinge, M. Gao, A. Romano-Rodriguez, H. Maes. and C. Claeys, "Silicon-on-insulator 'gate all-around device'," in Int. Electron Devices Meeting, 1990, pp. 595-598.
66. Y.-K. Choi, D. Ha, T.-J. King, and J. Bokor, "Reduction of gate-induced drain leakage (GIDL) current in single-gate ultra-thin body and double-gate FinFET devices," in Proc. Solid State Devices and Materials, 2002, pp. 140-141.
67. ISE TCAD: DESSIS, v7.0 User's Manual, Integrated Systems Engineering, Inc., San Jose, CA, 2001.