The Spacer/Replacer concept: A viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS

IEEE Electron Device Letters

Volumn 23, Issue 1, 2002, Pages 46-48

  Van Meer, Hans ^b   De Meyer, Kristin ^a,b  

^a IEEE

^b IMEC   (Belgium)

Author keywords

CMOSFETs; MOSFETs; Silicon on insulator technology

Indexed keywords

EPITAXIAL GROWTH; GATES (TRANSISTOR); POLYSILICON; SILICON ON INSULATOR TECHNOLOGY; THIN FILM TRANSISTORS; ULTRATHIN FILMS;

ULTRATHIN-FILM TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 0036165797     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.974808     Document Type: Article

References (9)

1. Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's
2. Optimization of series resistance in sub-0.2 μm SOI MOSFETs
3. 0.18-μm fully-depleted silicon-on-insulator MOSFET's
4. Improved LOCOS isolation for ultra thin 0.18 μm fully-depleted SOI CMOS
5. Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides
6. Reverse elevated source/drain (RESD) MOSFET for deep submicron CMOS
7. A new shift and ratio method for MOSFET channel-length extraction
8. Extraction of experimental mobility data for MOS devices