Advanced model and analysis of series resistance for CMOS scaling into nanometer regime - Part II: Quantitative analysis

IEEE Transactions on Electron Devices

Volumn 49, Issue 3, 2002, Pages 467-472

  Kim, Seong Dong ^a,b   Park, Cheol Min ^a,b   Woo, Jason C S ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

CMOS; High k dielectric; Modeling; Polysilicon gate depletion effect; Scaling; Series resistance; Ultra shallow junction

Indexed keywords

POLYSILICON GATE DEPLETION EFFECTS (PDE);

DIELECTRIC MATERIALS; DIFFUSION IN SOLIDS; ELECTRIC RESISTANCE; MATHEMATICAL MODELS; POLYSILICON; SCHOTTKY BARRIER DIODES; SEMICONDUCTOR DOPING;

CMOS INTEGRATED CIRCUITS;

EID: 0036494258     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.987118     Document Type: Article

References (12)

1. 25 nm CMOS design considerations
2. Material and process limits in silicon VLSI technology
3. Advanced model and analysis of series resistance for CMOS scaling into nanometer regime - Part I: Theoretical derivation
4. Test structure to investigate the series resistance components of source/drain structure
5. Analysis of the gate-voltage-dependent series resistance of MOSFET's
6. Measurements and modeling of MOSFET I-V characteristics with polysilicon depletion effect
7. The impact of high-k gate dielectric and metal gate electrodes on sub-100 nm MOSFET's
8. Source-side barrier effects with very high-k dielectrics in 50 nm Si MOSFET's
9. Series resistance of silicided ohmic contacts for nanoelecronics
10. Complementary silicide source/drain thin-body MOSFET's for the 20 nm gate length regime
11. x source/drain