-
1
-
-
0024170834
-
+ polysilicon in a dual-gate process
-
+ polysilicon in a dual-gate process," in IEDM Tech. Dig., 1988, pp. 238-241.
-
(1988)
IEDM Tech. Dig.
, pp. 238-241
-
-
Wong, C.Y.1
Sun, J.Y.C.2
Taur, Y.3
Oh, C.S.4
Angelucci, R.5
Davari, B.6
-
2
-
-
0025474417
-
+ polysilicon gates MOS devices
-
Aug.
-
+ polysilicon gates MOS devices," IEEE Trans. Electron Devices, vol. 37, pp. 1842-1851, Aug. 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, pp. 1842-1851
-
-
Pfiester, J.R.1
Baker, F.K.2
Mele, T.C.3
Tseng, H.H.4
Tobin, P.J.5
Hayden, J.D.6
Miller, J.W.7
Gunderson, C.D.8
Parrillo, L.C.9
-
3
-
-
0031140867
-
Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFETs
-
May
-
S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFETs," IEEE Electron Device Lett., vol. 18, pp. 209-211, May 1997.
-
(1997)
IEEE Electron Device Lett.
, vol.18
, pp. 209-211
-
-
Lo, S.H.1
Buchanan, D.A.2
Taur, Y.3
Wang, W.4
-
4
-
-
0031122158
-
CMOS scaling into the nanometer regime
-
Apr.
-
Y. Taur, D. Buchanan, W. Chen, D. J. Frank, K. I. Ismail, S.-H. Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J. C. Wann, S. J. Wind, and H.-S. Wong, "CMOS scaling into the nanometer regime," Proc. IEEE, vol. 85, pp. 486-504, Apr. 1997.
-
(1997)
Proc. IEEE
, vol.85
, pp. 486-504
-
-
Taur, Y.1
Buchanan, D.2
Chen, W.3
Frank, D.J.4
Ismail, K.I.5
Lo, S.-H.6
Sai-Halasz, G.A.7
Viswanathan, R.G.8
Wann, H.-J.C.9
Wind, S.J.10
Wong, H.-S.11
-
5
-
-
0032256253
-
25nm CMOS design consideration
-
Y. Taur, C. H. Wann, and D. J. Frank, "25nm CMOS design consideration," in IEDM Tech. Dig., 1998, pp. 789-792.
-
(1998)
IEDM Tech. Dig.
, pp. 789-792
-
-
Taur, Y.1
Wann, C.H.2
Frank, D.J.3
-
6
-
-
0033700304
-
Dual-metal gate technology for deep-submicron CMOS transistor
-
Q. Lu, Y. C. Yeo, P. Ranade, H. Takeuchi, T. J. King, C. Hu, S. C. Song, H. F. Luan, and D. L. Kwong, "Dual-metal gate technology for deep-submicron CMOS transistor," in Proc. Symp. VLSI Technology, 2000, pp. 72-73.
-
Proc. Symp. VLSI Technology, 2000
, pp. 72-73
-
-
Lu, Q.1
Yeo, Y.C.2
Ranade, P.3
Takeuchi, H.4
King, T.J.5
Hu, C.6
Song, S.C.7
Luan, H.F.8
Kwong, D.L.9
-
7
-
-
0035472007
-
x film
-
Oct.
-
x film," IEEE Trans. Electron Devices, vol. 48, pp. 2363-2369, Oct. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, pp. 2363-2369
-
-
Wakabayashi, H.1
Saito, Y.2
Takeuchi, K.3
Mogami, T.4
Kunio, T.5
-
8
-
-
0034796391
-
Electrical characteristics of TaSiN gate electrodes for dual gate Si-CMOS devices
-
Y. S. Suh, G. Heuss, H. Zong, S. N. Hong, and V. Misra, "Electrical characteristics of TaSiN gate electrodes for dual gate Si-CMOS devices," in Proc. IEEE Symp. VLSI Technology, 2001, pp. 47-48.
-
Proc. IEEE Symp. VLSI Technology, 2001
, pp. 47-48
-
-
Suh, Y.S.1
Heuss, G.2
Zong, H.3
Hong, S.N.4
Misra, V.5
-
9
-
-
0036160670
-
An adjustable work function technology using Mo gate for CMOS devices
-
Jan.
-
R. Lin, Q. Lu, P. Ranade, T. J. King, and C. Hu, "An adjustable work function technology using Mo gate for CMOS devices," IEEE Electron Device Lett., vol. 23, pp. 49-51, Jan. 2002.
-
(2002)
IEEE Electron Device Lett.
, vol.23
, pp. 49-51
-
-
Lin, R.1
Lu, Q.2
Ranade, P.3
King, T.J.4
Hu, C.5
-
10
-
-
0035714288
-
Properties of Ru-Ta alloys as gate electrodes for NMOS and PMOS silicon devices
-
H. Zhong, S. N. Hong, Y. S. Suh, H. Lazar, G. Heuss, and V. Misra, "Properties of Ru-Ta alloys as gate electrodes for NMOS and PMOS silicon devices," in IEDM Tech. Dig., 2001, pp. 432-435.
-
(2001)
IEDM Tech. Dig.
, pp. 432-435
-
-
Zhong, H.1
Hong, S.N.2
Suh, Y.S.3
Lazar, H.4
Heuss, G.5
Misra, V.6
-
11
-
-
0035716658
-
Robust ternary metal gate electrodes for dual gate CMOS devices
-
D. G. Park, T. H. Cha, K. Y. Lim, H. J. Cho, T. K. Kim, S. A. Jang, Y. S. Suh, V. Misra, I. S. Yeo, J S. Roh, J. W. Park, and H. K. Yoon, "Robust ternary metal gate electrodes for dual gate CMOS devices," in IEDM Tech. Dig., 2001, pp. 616-619.
-
(2001)
IEDM Tech. Dig.
, pp. 616-619
-
-
Park, D.G.1
Cha, T.H.2
Lim, K.Y.3
Cho, H.J.4
Kim, T.K.5
Jang, S.A.6
Suh, Y.S.7
Misra, V.8
Yeo, I.S.9
Roh, J.S.10
Park, J.W.11
Yoon, H.K.12
-
12
-
-
0036540912
-
Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion
-
Apr.
-
I. Polishchuk, P. Ranade, T. J. King, and C. Hu, "Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion," IEEE Electron Device Lett., vol. 23, pp. 200-202, Apr. 2002.
-
(2002)
IEEE Electron Device Lett.
, vol.23
, pp. 200-202
-
-
Polishchuk, I.1
Ranade, P.2
King, T.J.3
Hu, C.4
-
13
-
-
0037260482
-
Investigation of Cu/TaNx metal gate for metal-oxide-silicon devices
-
Jan.; to be published
-
B. Y. Tsui and C. F. Huang, "Investigation of Cu/TaNx metal gate for metal-oxide-silicon devices," J. Electrochem. Soc., Jan. 2003, to be published.
-
(2003)
J. Electrochem. Soc.
-
-
Tsui, B.Y.1
Huang, C.F.2
-
14
-
-
34547417516
-
Charge transfer in alloys: AgAu
-
C. D. Gelatt, Jr. and H. Ehrenreich, "Charge transfer in alloys: AgAu," Phys. Rev. B, vol. 10, no. 2, pp. 398-415, 1974.
-
(1974)
Phys. Rev. B
, vol.10
, Issue.2
, pp. 398-415
-
-
Gelatt C.D., Jr.1
Ehrenreich, H.2
-
15
-
-
18344413125
-
Work function of binary alloys
-
R. Ishii, K. Matsumura, A. Sakai, and T. Sakata, "Work function of binary alloys," Appl. Surf. Sci., vol. 169-170, pp. 658-661, 2001.
-
(2001)
Appl. Surf. Sci.
, vol.169-170
, pp. 658-661
-
-
Ishii, R.1
Matsumura, K.2
Sakai, A.3
Sakata, T.4
-
17
-
-
0034453428
-
Gate length scaling and threshold voltage control of double-gate MOSFETs
-
L. Chang, S. Tang, T. J. King, J. Bokor, and C. Hu, "Gate length scaling and threshold voltage control of double-gate MOSFETs," in IEDM Tech. Dig., 2000, pp. 719-722.
-
(2000)
IEDM Tech. Dig.
, pp. 719-722
-
-
Chang, L.1
Tang, S.2
King, T.J.3
Bokor, J.4
Hu, C.5
-
18
-
-
0021619799
-
Interaction between Ti and SiO2
-
C. Y. Ting, M. Wittmer, S. S. Iyer, and S. B. Brodsky, "Interaction between Ti and SiO2," J. Electrochem. Soc., vol. 131, no. 12, pp. 2934-2938, 1984.
-
(1984)
J. Electrochem. Soc.
, vol.131
, Issue.12
, pp. 2934-2938
-
-
Ting, C.Y.1
Wittmer, M.2
Iyer, S.S.3
Brodsky, S.B.4
-
19
-
-
0035337187
-
Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric
-
May
-
Y. C. Yeo, Q. Lu, P. Ranade, H. Takeuchi, K. J. Yang, I. Polishchuk, T. J. King, C. Hu, S. C. Song, H. F. Luan, and D. L. Kwong, "Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric," IEEE Electron Device Lett., vol. 22, pp. 227-229, May 2002.
-
(2002)
IEEE Electron Device Lett.
, vol.22
, pp. 227-229
-
-
Yeo, Y.C.1
Lu, Q.2
Ranade, P.3
Takeuchi, H.4
Yang, K.J.5
Polishchuk, I.6
King, T.J.7
Hu, C.8
Song, S.C.9
Luan, H.F.10
Kwong, D.L.11
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