Spacer FinFET: Nanoscale double-gate CMOS technology for the terabit era

Solid-State Electronics

Volumn 46, Issue 10, 2002, Pages 1595-1601

  Choi, Yang Kyu ^a   King, Tsu Jae ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; DRY ETCHING; FABRICATION; MOSFET DEVICES; PHOTOLITHOGRAPHY; SEMICONDUCTING FILMS;

SPACER LITHOGRAPHY;

SOLID STATE DEVICE STRUCTURES;

EID: 0036779146     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(02)00111-9     Document Type: Conference Paper

References (15)

1. FinFET - A self-aligned double-gate MOSFET scalable to 20 nm
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3. Nanoscale CMOS
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5. Gate length scaling and threshold voltage control of double-gate MOSFETs
6. Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime
7. Exposure of 38 nm period grating patterns with extreme ultraviolet interferometric lithography
8. Threshold voltage increase by quantum mechanical narrow channel effect in ultra-narrow MOSFETs
9. Threshold voltage shift by quantum confinement in ultra-thin body device
10. 2
11. Patterning sub-30-nm MOSFET Gate with I-line lithography
12. Hot-carrier effects in fully-depleted SOI nMOSFETs
13. Characterization of surface mobility on the sidewalls of dry-etched trenches