The design of dual work function CMOS transistors and circuits using silicon nanowire technology

IEEE Transactions on Nanotechnology

Volumn 6, Issue 3, 2007, Pages 291-302

  Bindal, Ahmet ^a,b   Naresh, Adithya ^b   Yuan, Pearl ^b   Nguyen, Kim K ^b   Hamedi Hagh, Sotoudeh ^a,b  

^a IEEE   (United States)

^b SAN JOSE STATE UNIVERSITY   (United States)

Author keywords

Low power very large scale integration (VLSI); Metal gate transistors; Nanowire transistors; Vertical silicon transistors

Indexed keywords

METAL-GATE TRANSISTORS; NANOWIRE TRANSISTORS; VERTICAL SILICON TRANSISTORS;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; NAND CIRCUITS; NANOWIRES; VLSI CIRCUITS;

TRANSISTORS;

EID: 34248653757     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2007.894355     Document Type: Article

References (60)

1. C. P. Collier, E. W. Wong, M. Belohradsky, F. M. Raymo, J. F. Stoddard, P. J. Kuekes, R. S. Williams, and J. R. Heath, "Electronically configurable molecular-based logic gates," Science, vol. 285, pp. 391-394, 1999.
2. S. C. Goldstein and M. Budiu, "Nanofabrics: Spatial computing using molecular electronics," in Proc. 28th Annu. Int. Symp. Computer Architecture, 2001, pp. 178-189.
3. K. Kim, K. K. Das, R. V. Joshi, and C.-T. Chuang, "Leakage power analysis of 25-nm double-gate CMOS devices and circuits," IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 980-986, May 2005.
4. G. Tsutsui, M. Saitoh, T. Nagumo, and T. Hiramoto, "Impact of SOI thickness fluctuation on threshold voltage variation in ultrathin body SOI MOSFETs," IEEE Trans. Nanotechnol., vol. 4, no. 3, pp. 369-373, May 2005.
5. R. Zhang, K. Roy, and D. B. Janes, "Double-gate fully-depleted SOI transistors for low-power high performance nano-scale circuit design," in Proc. 2001 Int. Symp. Low Power Electronics and Design, pp. 213-218.
6. G. V. Reddy and M. J. Kumar, "A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two dimensional analytical modeling and simulation," IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 260-268, Mar. 2005.
7. A. Kumar, J. Kedzierski, and S. E. Laux, "Quantum-based simulation analysis of scaling in ultrathin body device structures," IEEE Trans. Electron Devices, vol. 52, no. 4, pp. 614-617, Apr. 2005.
8. D. Vasileska and S. S. Ahmed, "Narrow-Width SOI devices: The role of quantum-mechanical size quantization effect and unintentional doping on device operation," IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 227-236, Feb. 2005.
9. J.-W. Yang and J. Fossum, "On the feasibility of nanoscale triple-gate CMOS transistors," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1159-1164, Jun. 2005.
10. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm length," in Tech. Dig. IEDM, 2002, pp. 251-254.
11. Y.-K. Choi, L. Chang, P. Ranade, J.-S. Lee, D. Ha, S. Balasubramanian, A. Agarwal, M. Ameen, T.-J. King, and J. Bokor, "FinFET process refinements for improved mobility and gate work function engineering," in Tech. Dig. IEDM, 2002, pp. 259-262.
12. R. S. Wagner and W. C. Ellis, "Vapor-Liquid-Solid mechanism of single crystal growth," Appl. Phys. Lett., vol. 4, no. 5, pp. 89-90, 1964.
13. T. I. Kamins, S. R. Williams, D. P. Basile, T. Hesjedal, and J. S. Harris, "Ti-catalyzed Si nanowires by chemical vapor deposition: Microscopy and growth mechanisms," J. Appl. Phys., vol. 89, no. 2, pp. 1008-1016, 2001.
14. M. S. Islam, S. Sharma, T. I. Kamins, and R. S. Williams, "Ultra-high-Density silicon nanobridges formed between two vertical silicon surfaces," Nanotechnology, vol. 15, pp. L5-L8, 2004.
15. T. Kikuchi, S. Moriya, Y. Nakatsuka, H. Matsuoka, K. Nakazato, A. Nishida, H. Chakihara, M. Matsuoka, and M. Moniwa, "A new vertically stacked poly-Si MOSFET for 533 MHz high speed 64 mbit SRAM," in Tech. Dig. IEDM, 2004, pp. 923-926.
16. H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka, "Impact of surrounding gate transistor (SGT) for ultra-high-density LSI," IEEE Trans. Election Devices, vol. 38, no. 3, pp. 573-578, Mar. 1991.
17. Y. Zheng, C. Rivas, R. Lake, K. Alam, T. B. Boykin, and G. Klimeck, "Electronic properties of silicon nanowires," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1097-1103, Jun. 2005.
18. S. Miyano, M. Hirose, and F. Masuoka, "Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA)," IEEE Trans. Electron Devices, vol. 39, no. 8, pp. 1876-1881, Aug. 1992.
19. C. Dwyer, L. Vicci, J. Poulton, D. Erie, R. Superfine, S. Washburn, and R. M. Taylor, "The design of DNA self-assembled computing circuitry," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 11, pp. 1214-1220, Nov. 2004.
20. C. Dwyer, L. Vicci, and R. M. Taylor, "Performance simulation of nanoscale silicon rod field-effect transistor logic," IEEE Trans. Nanotechnol., vol. 2, no. 2, pp. 69-74, 2003.
21. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
22. Y.-K. Choi, D. Ha, T.-J. King, and J. Bokor, "Investigation of gate induced drain leakage (GIDL) current in thin body devices: Single-gate ultrathin body, symmetrical double gate, and asymmetrical double gate MOSFETs," Jpn. J. Appl. Phys., vol. 42, pp. 2073-2076, 2003.
23. O. Semenov, A. Pradzynski, and M. Sachdev, "Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits," IEEE Trans. Sem. Manufac., vol. 15, no. 1, pp. 9-18, 2002.
24. A. Wettstein, A. Schenk, and W. Fichtner, "Quantum device-simulation with density gradient model on unstructured grids," IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 279-283, 2001.
25. C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 7, no. 11, pp. 1164-1171, 1988.
26. D. M. Caughey and R. E. Thomas, "Carrier mobilities in silicon empirically related to doping and field," Proc. IEEE, vol. 55, no., pp. 2192-2193, 1967.
27. N. D. Arora, J. R. Hauser, and D. J. Roulston, "Electron and hole mobilities in silicon as a function of concentration and temperature," IEEE Trans. Electron Devices, vol. ED-29, pp. 292-295, 1982.
28. S. Serberherr, "Process and device modeling for VLSI," Microelec. Reliab., vol. 24, no. 2, pp. 225-257, 1984.
29. Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko, and Y. C. Cheng, "Threshold voltage model for deep-submicrometer mosfets," IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 86-95, 1993.
30. G. Sery, S. Borkar, and V. De, "Life is CMOS: Why chase the life after," Proc. Design Automation Conf., pp. 78-83, 2002.
31. T.-K. Chiang, "New current-voltage model for surrounding-gate metal-oxide-semiconductor field effect transistors," Jap. J. Appl. Phys., vol. 44, no. 9A, pp. 6446-6451, 2005.
32. Q. Chen, E. M. Harrell, and J. D. Meindl, "A physical short-channel threshold voltage model for undoped symmetric double-gate mosfets," IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1631-1637, 2003.
33. F. Boeuf et al., "A conventional 45 nm CMOS node low-cost platform for general purpose and low power applications," in Tech. Dig. IEDM, 2004, pp. 425-428.
34. T. Numata et al., "Performance enhancement of partially and fully-depleted strained-SOI MOSFETs and characterization of strained-si device parameters," in Tech. Dig. IEDM, 2004, pp. 177-180.
35. A. Shima, H. Ashihara, A. Hiraiwa, T. Mine, and Y. Goto, "Ultra-shallow junction formation by self-limiting LTP and its application to sub-65 nm node MOSFETs," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1165-1171, 2005.
36. H. C. H. Wang et al., "Low power device technology with SiGe channel, HfSiON, and Poly-Si gate," in Tech. Dig. IEDM, 2004, pp. 161-164.
37. Z. Luo et al., "High performance and low power transistors integrated in 65 nm bulk CMOS technology," in Tech. Dig. IEDM, 2004, pp. 661-664.
38. N. Lindert, Y. K. Choi, L. Chang, E. Anderson, and W. C. Lee, "Quasiplanar nMOS FinFETs with sub-100 nm gate lengths," in Proc. Device Research Conf., 2001, pp. 26-27.
39. Y. K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, and E. Anderson, "Sub-20 nm CMOS FinFET technologies," in Tech. Dig. IEDM, 2001, pp. 421-424.
40. H. Wakabayashi et al., "Transport propeities of sub-10 nm planar-bulk-CMOS devices," in Tech. Dig. IEDM, 2004, pp. 429-432.
41. 2 SRAM cell," in Tech. Dig. IEDM, 2004, pp. 657-660.
42. J. Kedzierski, D. M. Dried, E. J. Nowak, T. Kanarsky, and J. H. Rankin, "High performance symmetric-gate and CMOS compatible Vt asymmetric-gate FinFET devices," in Tech. Dig. IEDM, 2001, pp. 437-440.
43. F. L. Yang, H. Y. Chen, F. C. Chen, and Y. L. Chan, "35 nm CMOS FinFETs," in Five. Symp. VLSI Tech., 2001, pp. 104-105.
44. A. Concannon, F. Piccinini, A. Mathewson, and C. Lombardi, "The numerical simulation of substrate and gate currents in MOS and EPROMS," in Tech. Dig. IEDM, 1995, pp. 289-292.
45. M. J. V. Dort, P. H. Woerlee, and A. J. Walker, "A simple model for quantisation effects in heavily-doped silicon MOSFETs at inversion conditions," Solid State Electron., vol. 37, no. 3, pp. 411-414, 1994.
46. N. Srivastava and K. Banerjee, "A comparative scaling analysis of metallic and carbon nanotube interconnections for nanometer scale VLSI technologies," in Proc. 21st. Int. Multilevel Interconnect Conf., 2004, pp. 393-398.
47. P. Moon, V. Dubin, S. Johnston, J. Leu, K. Raol, and C. Wu, "Process roadmap and challenges for metal barriers," in Tech. Dig, IEDM, 2003, pp. 841-844.
48. M. Tada et al., "A 65 nm-Node, Cu interconnect technology using porous SiOCH film (k = 2.5) covered with ultra-thin, low-k pore seal (k = 2.7)," in Tech. Dig. IEDM, 2003, pp. 845-848.
49. 2 6T-SRAM cell and robost hybrid-ULK/Cu interconnects for mobile multimedia applications," in Tech. Dig. IEDM, 2003, pp. 285-288.
50. S. Kondo, B. U. Yoon, S. Tokitoh, K. Misawa, S. Sone, H. J. Shin, N. Ohashi, and N. Kobayashi. "Low-Pressure CMP for 300-mm ultra low-k (k = 1.6 - 1.8)/Cu integration," in Tech. Dig. IEDM, 2003, pp. 151-154.
51. A. Isobayashi, Y. Enomoto, H. Yamada, S. Takahashi, and S. Kadomura, "Thermally robost Cu interconnects with Cu-Ag alloy for sub 45 nm node," in Tech. Dig. IEDM, 2004, pp. 953-956.
52. G. B. Alers, J. Sukamto, S. Park, G. Harm, and J. Reid, "Containing the finite size effect in copper lines," Semicond. Int., vol. 29, no. 5, pp. 38-42, 2006.
53. M. Alioto and G. Palumbo, "Analysis and comparison on full adder block in submicron technology," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 6, pp. 806-823, Dec. 2002.
54. C. H. Chang, J. Gu, and M. Zhang, "A review of 0.18-μm full adder performances for tree structured arithmetic circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686-695, Jun. 2005.
55. A. M. Shams, T. K. Darwish, and M. A. Bayoumi, "Performance analysis of low-power 1-Bit CMOS full adder cells," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp. 20-29, Feb. 2002.
56. M. Sayed and W. Badawy, "Performance analysis of single-bit full adder cells using 0.18, 0.25 and 0.35 μm CMOS technologies," in IEEE Int. Symp. Circuits Sys., 2002, pp. 559-562.
57. C. H. Chang, M. Zhang, and J. Gu, "A novel low power low voltage full adder cell," in Proc. 3rd. Int. Symp, Image and Signal Processing and Analysis, 2003, pp. 454-458.
58. A. A. Khatibzade and K. Raahemifar, "A study and comparison of full adder cells based on the standard static CMOS logic," in Proc. Can. Conf. Electrical and Computer Engineering, 2004, pp. 2139-2142.
59. S. Goel, S. Gollamudi, A. Kumar, and M. Bayoumi, "On the design of low-energy hybrid CMOS 1-Bit full adder cells," in Proc. 47th. Midwest Symp. Circuits and Systems, 2004, pp. 209-212.
60. A. Bindal and S. Hamedi-Hagh, "The design and analysis of dynamic NMOSFET/PMESFET logic using silicon nano-wire technology," Semicond. Sci. Technol., vol. 21, pp. 1002-1012, 2006.