-
2
-
-
0000434281
-
Ti-catalyzed Si nanowires by chemical vapour deposition: Microscopy and growth mechanisms
-
Kamins T I, Williams S R, Basile D P, Hesjedal T and Harris J S 2001 Ti-catalyzed Si nanowires by chemical vapour deposition: microscopy and growth mechanisms J. Appl. Phys. 89 1008-16
-
(2001)
J. Appl. Phys.
, vol.89
, Issue.2
, pp. 1008-1016
-
-
Kamins, T.I.1
Williams, S.R.2
Basile, D.P.3
Hesjedal, T.4
Harris, J.S.5
-
3
-
-
2642566816
-
Ultrahigh-density silicon nanobridges formed between two vertical silicon surfaces
-
Islam M S, Sharma S, Kamins T I and Williams R S 2004 Ultrahigh-density silicon nanobridges formed between two vertical silicon surfaces Nanotechnology 15 L5-8
-
(2004)
Nanotechnology
, vol.15
, Issue.5
-
-
Islam, M.S.1
Sharma, S.2
Kamins, T.I.3
Williams, R.S.4
-
4
-
-
0037912948
-
Growth of silicon nanowires via gold/silane vapor-liquid-solid reaction
-
Westwater J, Gosain D P, Tomiya S, Usui S and Ruda H 1997 Growth of silicon nanowires via gold/silane vapor-liquid-solid reaction J. Vac. Sci. Technol. B 15 554-7
-
(1997)
J. Vac. Sci. Technol.
, vol.15
, Issue.3
, pp. 554-557
-
-
Westwater, J.1
Gosain, D.P.2
Tomiya, S.3
Usui, S.4
Ruda, H.5
-
5
-
-
21644470779
-
A new vertically stacked poly-Si MOSFET for 533 MHz high speed 64 Mbit SR AM
-
Kikuchi T, Moriya S, Nakatsuka Y, Matsuoka H, Nakazato K, Nishida A, Chakihara H, Matsuoka M and Moniwa M 2004 A new vertically stacked poly-Si MOSFET for 533 MHz high speed 64 Mbit SR AM IEDM: International Electron Devices Meeting pp 923-6
-
(2004)
IEDM: International Electron Devices Meeting
, pp. 923-926
-
-
Kikuchi, T.1
Moriya, S.2
Nakatsuka, Y.3
Matsuoka, H.4
Nakazato, K.5
Nishida, A.6
Chakihara, H.7
Matsuoka, M.8
Moniwa, M.9
-
6
-
-
28144432921
-
Nano-wires for room temperature operated hybrid CMOS-NANO integrated circuits
-
Ecoffey S, Pott V, Bouvet D, Mazza M, Mahapatra S, Schmid A, Leblebici Y, Declercq M J and Ionescu A M 2005 Nano-wires for room temperature operated hybrid CMOS-NANO integrated circuits IEEE Int. Solid State Circuit Conf. vol 597 pp 260-1
-
(2005)
IEEE Int. Solid State Circuit Conf.
, vol.597
, pp. 260-261
-
-
Ecoffey, S.1
Pott, V.2
Bouvet, D.3
Mazza, M.4
Mahapatra, S.5
Schmid, A.6
Leblebici, Y.7
Declercq, M.J.8
Ionescu, A.M.9
-
7
-
-
0026122410
-
Impact of surrounding gate transistor (SGT) for ultra-high-density LSI
-
Takato H, Sunouchi K, Okabe N, Nitayama A, Hieda K, Horiguchi F and Masuoka F 1991 Impact of surrounding gate transistor (SGT) for ultra-high-density LSI IEEE Trans. Electron Devices 38 573-78
-
(1991)
IEEE Trans. Electron Devices
, vol.38
, Issue.3
, pp. 573-578
-
-
Takato, H.1
Sunouchi, K.2
Okabe, N.3
Nitayama, A.4
Hieda, K.5
Horiguchi, F.6
Masuoka, F.7
-
8
-
-
0038161696
-
High performance silicon nanowire field effect transistors
-
Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149-52
-
(2003)
Nano Lett.
, vol.3
, Issue.2
, pp. 149-152
-
-
Cui, Y.1
Zhong, Z.2
Wang, D.3
Wang, W.U.4
Lieber, C.M.5
-
9
-
-
21044456044
-
Electronic properties of silicon nanowires
-
Zheng Y, Rivas C, Lake R, Alam K, Boykin T B and Klimeck G 2005 Electronic properties of silicon nanowires IEEE Trans. Electron Devices 52 1097-103
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.6
, pp. 1097-1103
-
-
Zheng, Y.1
Rivas, C.2
Lake, R.3
Alam, K.4
Boykin, T.B.5
Klimeck, G.6
-
11
-
-
0026909715
-
Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA)
-
Miyano S, Hirose M and Masuoka F 1992 Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA) IEEE Trans. Electron Devices 39 1876-81
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.8
, pp. 1876-1881
-
-
Miyano, S.1
Hirose, M.2
Masuoka, F.3
-
12
-
-
9244243065
-
The design of DNA self-assembled computing circuitry
-
Dwyer C, Vicci L, Poulton J, Erie D, Superfine R, Washburn S and Taylor R M 2004 The design of DNA self-assembled computing circuitry IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12 1214-20
-
(2004)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.12
, Issue.11
, pp. 1214-1220
-
-
Dwyer, C.1
Vicci, L.2
Poulton, J.3
Erie, D.4
Superfine, R.5
Washburn, S.6
Taylor, R.M.7
-
13
-
-
3042742837
-
Performance simulation of nanoscale silicon rod field-effect transistor logic
-
Dwyer C, Vicci L and Taylor R M 2003 Performance simulation of nanoscale silicon rod field-effect transistor logic IEEE Trans. Nanotechnol. 2 69-74
-
(2003)
IEEE Trans. Nanotechnol.
, vol.2
, Issue.2
, pp. 69-74
-
-
Dwyer, C.1
Vicci, L.2
Taylor, R.M.3
-
14
-
-
15844407150
-
Benchmarking nanotechnology for high-performance and low power logic transistor applications
-
Chau R, Datta S, Doczy M, Doyle B, Jin B, Kavalieros J, Majumdar A, Metz M and Radosavljevic M 2005 Benchmarking nanotechnology for high-performance and low power logic transistor applications IEEE Trans. Nanotechnol. 4 153-8
-
(2005)
IEEE Trans. Nanotechnol.
, vol.4
, Issue.2
, pp. 153-158
-
-
Chau, R.1
Datta, S.2
Doczy, M.3
Doyle, B.4
Jin, B.5
Kavalieros, J.6
Majumdar, A.7
Metz, M.8
Radosavljevic, M.9
-
15
-
-
0033115380
-
Nanoscale CMOS
-
Wong H-S P, Frank D, Solomon P M, Wann C H J and Welser J J 1990 Nanoscale CMOS Proc. IEEE 87 537-70
-
(1990)
Proc. IEEE
, vol.87
, Issue.4
, pp. 537-570
-
-
Wong, H.-S.P.1
Frank, D.2
Solomon, P.M.3
Wann, C.H.J.4
Welser, J.J.5
-
16
-
-
0019049847
-
Design and characteristics of the lightly doped drain-source (LDD) insulated gate field effect transistor
-
Ogura S, Tsang P J, Walker W W, Critchlow D L and Shepard J F 1980 Design and characteristics of the lightly doped drain-source (LDD) insulated gate field effect transistor IEEE Trans. Electron Devices 27 1359-67
-
(1980)
IEEE Trans. Electron Devices
, vol.27
, pp. 1359-1367
-
-
Ogura, S.1
Tsang, P.J.2
Walker, W.W.3
Critchlow, D.L.4
Shepard, J.F.5
-
19
-
-
0026837568
-
Simulation of ultra small GaAs MESFET using quantum moment equations
-
Zhou J R and Ferry D K 1992 Simulation of ultra small GaAs MESFET using quantum moment equations IEEE Trans. Electron Devices 39 473-8
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.3
, pp. 473-478
-
-
Zhou, J.R.1
Ferry, D.K.2
-
20
-
-
0026908536
-
Simulation of ultra small GaAs MESFET using quantum moment equations: II. Velocity overshoot
-
Zhou J R and Ferry D K 1992 Simulation of ultra small GaAs MESFET using quantum moment equations: II. Velocity overshoot IEEE Trans. Electron Devices 39 1793-6
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.8
, pp. 1793-1796
-
-
Zhou, J.R.1
Ferry, D.K.2
-
21
-
-
0028515347
-
In-plane transport properties of Si/Si(1 - X)Ge(x) structure and its FET performance by computer simulation
-
Yamada T, Zhou J R, Miyata H and Ferry D K 1994 In-plane transport properties of Si/Si(1 - x)Ge(x) structure and its FET performance by computer simulation IEEE Trans. Electron Devices 41 1513-22
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, Issue.9
, pp. 1513-1522
-
-
Yamada, T.1
Zhou, J.R.2
Miyata, H.3
Ferry, D.K.4
-
22
-
-
0035249575
-
Quantum device-simulation with the density-gradient model on unstructured grids
-
Wettstein A, Schenk A and Fichtner W 2001 Quantum device-simulation with the density-gradient model on unstructured grids IEEE Trans. Electron Devices 48 279-83
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, Issue.2
, pp. 279-283
-
-
Wettstein, A.1
Schenk, A.2
Fichtner, W.3
-
24
-
-
31544469237
-
New current-voltage model for surrounding-gate metal-oxide-semiconductor field effect transistors
-
Chiang T-K 2005 New current-voltage model for surrounding-gate metal-oxide-semiconductor field effect transistors Japan. J. Appl. Phys. 44 6446-51
-
(2005)
Japan. J. Appl. Phys.
, vol.44
, pp. 6446-6451
-
-
Chiang, T.-K.1
-
25
-
-
0027667486
-
Fabrication of extremely thin silicon on insulator for fully-depleted CMOS applications
-
Bindal A, Rovedo N, Restivo J, Galli C and Ogura S 1993 Fabrication of extremely thin silicon on insulator for fully-depleted CMOS applications Thin Solid Films 232 105-09
-
(1993)
Thin Solid Films
, vol.232
, Issue.1
, pp. 105-109
-
-
Bindal, A.1
Rovedo, N.2
Restivo, J.3
Galli, C.4
Ogura, S.5
-
26
-
-
0023366571
-
An analytic I-V model for lightly doped drain (LDD) MOSFET devices
-
Huang G-S and Wu C-Y 1987 An analytic I-V model for lightly doped drain (LDD) MOSFET devices IEEE Trans. Electron Devices 34 1311-21
-
(1987)
IEEE Trans. Electron Devices
, vol.34
, pp. 1311-1321
-
-
Huang, G.-S.1
Wu, C.-Y.2
-
28
-
-
23744492075
-
A review of 0.18-νm full adder performances for tree structured arithmetic circuits
-
Chang C H, Gu J and Zhang M 2005 A review of 0.18-νm full adder performances for tree structured arithmetic circuits IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 13 686-95
-
(2005)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.13
, Issue.6
, pp. 686-695
-
-
Chang, C.H.1
Gu, J.2
Zhang, M.3
-
31
-
-
0036296689
-
Performance analysis of single-bit full adder cells using 0.18, 0.25 and 0.35 νm CMOS technologies
-
Sayed M and Badawy W 2002 Performance analysis of single-bit full adder cells using 0.18, 0.25 and 0.35 νm CMOS technologies IEEE Int. Symp. Circuits Syst. 559-62
-
(2002)
IEEE Int. Symp. Circuits Syst.
, pp. 559-562
-
-
Sayed, M.1
Badawy, W.2
|